// 2024-1-3  姜青羊 
// 与非门

`timescale 1ns/10ps
module nand (
                        A,
                        B,
                        Y
                    );

input                   A,B;
output                  Y;

assign                  Y=~(A&B);

endmodule


//------testbench---------

module tb_nand ();

reg                     a,b;
wire                    y;

initial begin
                        a<=0; b<=0;
            #10         a<=0; b<=1;
            #10         a<=1; b<=0;
            #10         a<=1; b<=1;
                        $stop;
end

nand u_nand (
                        .A(a),
                        .B(b),
                        .Y(y)
                    );
    
endmodule