1 Star 0 Fork 0

打野/Verilog练习代码

加入 Gitee
与超过 1200万 开发者一起发现、参与优秀开源项目,私有仓库也完全免费 :)
免费加入
文件
克隆/下载
practice_10.26.v 1.46 KB
一键复制 编辑 原始数据 按行查看 历史
打野 提交于 2年前 . 2023-10-26
//2023-10-26 姜青羊
//case语句实现多路选择逻辑 ,tb写的更简便一些
/*module tb_fn_sw ();
reg aa,bb,ss;
wire yy;
initial begin
ss = 2'b00; aa = 0; bb = 0;
#10 ss = 2'b00; aa = 0; bb = 1;
#10 ss = 2'b00; aa = 1; bb = 0;
#10 ss = 2'b00; aa = 1; bb = 1;
#10 ss = 2'b01; aa = 0; bb = 0;
#10 ss = 2'b01; aa = 0; bb = 1;
#10 ss = 2'b01; aa = 1; bb = 0;
#10 ss = 2'b01; aa = 1; bb = 1;
#10 ss = 2'b10; aa = 0; bb = 0;
#10 ss = 2'b10; aa = 0; bb = 1;
#10 ss = 2'b10; aa = 1; bb = 0;
#10 ss = 2'b10; aa = 1; bb = 1;
#10 ss = 2'b11; aa = 0; bb = 0;
#10 ss = 2'b11; aa = 0; bb = 1;
#10 ss = 2'b11; aa = 1; bb = 0;
#10 ss = 2'b11; aa = 1; bb = 1;
$stop;
end
fn_sw u_fn_sw (
.a(aa),
.b(bb),
.sel(ss),
.y(yy)
);
endmodule
*/
module tb_fn_sw ();
reg[3:0] absel;
wire yy;
initial begin
absel = 4'b0000;
#200 $stop;
end
always #10 absel = absel+1;
fn_sw u_fn_sw (
.a(aa),
.b(bb),
.sel(ss),
.y(yy)
);
endmodule
Loading...
马建仓 AI 助手
尝试更多
代码解读
代码找茬
代码优化
1
https://gitee.com/fight_wild/verilog-code.git
git@gitee.com:fight_wild/verilog-code.git
fight_wild
verilog-code
Verilog练习代码
master

搜索帮助