//2023-11-6 
//
`timescale 1ns/10ps
module inv (
                A,
                Y
           );

input           A;
output          Y;

assign          Y=~A;
    
endmodule

module tb_inv ();

reg              a;
wire             y;

initial begin
                 a=0;
         #10     a=1;
         #10     a=0;
         #10     a=1;
                 $stop;
end


inv u_inv (
                .A(a),
                .Y(y)
           );

endmodule



//ת

module comp_conv (
                    a,
                    a_comp
                 );

input[7:0]          a;
output[7:0]         a_comp;

wire[6:0]           b;
wire[7:0]           y;


assign              b=~a[6:0];
assign              y[6:0]=b+1;
assign              y[7]=a[7];

assign              a_comp=a[7]?y:a;
    
endmodule