//2024-2-10 姜青羊
//计数器默写

`timescale 1ns/10ps
module counter (
                    clk,
                    res,
                    y
                );

input               clk,res;
output[7:0]         y;

reg[7:0]            y;
wire[7:0]           sum;

assign              sum=y+1;

always @(posedge clk or negedge res) begin
      if(~res)
         y<=0;
      else
         y<=sum;
end    

endmodule

//------testbench--------

module tb_counter ();

reg                 clk,res;
wire[7:0]           y;

initial begin
                   clk<=0; res<=0;
            #17    clk<=1;
            #6000  $stop;
end
       
always      #5     clk=~clk;

counter u_counter (
                    .clk(clk),
                    .res(res),
                    .y(y)
                );

endmodule