//2024-2-24 姜青羊
//日常练习

/*`timescale 1ns/10ps
module inverter (
                        A,
                        Y
                    );

input                   A;
output                  Y;

assign                  Y=~A;

endmodule

//-----testbench-----
module tb_inverter ( );

reg                     a;
wire                    y;

inverter u_inverter (
                        .A(a),
                        .Y(y)
                      );

initial begin
                        a=0;
                #10     a=1;
                #10     a=0;
                #10     a=1;
                        $stop;
                
end

endmodule*/


module counter (
                            clk,
                            res,
                            y
                        );

input                       clk,res;
output[7:0]                 y;

wire[7:0]                   sum;
reg[7:0]                    y;

assign                      y=sum+1;

always @(posedge clk or negedge res) begin
    if(~res) 
       y<=0; 
    else
       y<=sum;
end

    
endmodule