//2024-2-29 姜青羊
//日常练习

module comp_conv (
                        a,
                        a_comp
                    );

input[7:0]              a;
output[7:0]             a_comp;

wire[6:0]               b;

assign                  b=~a[6:0]+1;

assign                  a_comp=a[7]?b:a;
    
endmodule


//------testbench-------