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/*
* Copyright (c) 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "board.h"
#include "hpm_uart_drv.h"
#include "hpm_gptmr_drv.h"
#include "hpm_lcdc_drv.h"
#include "hpm_i2c_drv.h"
#include "hpm_gpio_drv.h"
#include "hpm_femc_drv.h"
#include "pinmux.h"
#include "hpm_pmp_drv.h"
#include "hpm_clock_drv.h"
#include "hpm_sysctl_drv.h"
#include "hpm_sdxc_drv.h"
#include "hpm_sdxc_soc_drv.h"
#include "hpm_pllctl_drv.h"
#include "hpm_pwm_drv.h"
#include "hpm_pcfg_drv.h"
#include "hpm_enet_drv.h"
#include "hpm_sdk_version.h"
static bool invert_led_level;
/**
* @brief FLASH configuration option definitions:
* option[0]:
* [31:16] 0xfcf9 - FLASH configuration option tag
* [15:4] 0 - Reserved
* [3:0] option words (exclude option[0])
* option[1]:
* [31:28] Flash probe type
* 0 - SFDP SDR / 1 - SFDP DDR
* 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
* 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
* 6 - OctaBus DDR (SPI -> OPI DDR)
* 8 - Xccela DDR (SPI -> OPI DDR)
* 10 - EcoXiP DDR (SPI -> OPI DDR)
* [27:24] Command Pads after Power-on Reset
* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
* [23:20] Command Pads after Configuring FLASH
* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
* [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
* 0 - Not needed
* 1 - QE bit is at bit 6 in Status Register 1
* 2 - QE bit is at bit1 in Status Register 2
* 3 - QE bit is at bit7 in Status Register 2
* 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
* [15:8] Dummy cycles
* 0 - Auto-probed / detected / default value
* Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
* [7:4] Misc.
* 0 - Not used
* 1 - SPI mode
* 2 - Internal loopback
* 3 - External DQS
* [3:0] Frequency option
* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
*
* option[2] (Effective only if the bit[3:0] in option[0] > 1)
* [31:20] Reserved
* [19:16] IO voltage
* 0 - 3V / 1 - 1.8V
* [15:12] Pin group
* 0 - 1st group / 1 - 2nd group
* [11:8] Connection selection
* 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
* [7:0] Drive Strength
* 0 - Default value
* option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
* JESD216)
* [31:16] reserved
* [15:12] Sector Erase Command Option, not required here
* [11:8] Sector Size Option, not required here
* [7:0] Flash Size Option
* 0 - 4MB / 1 - 8MB / 2 - 16MB
*/
#if defined(FLASH_XIP) && FLASH_XIP
__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000007, 0xE, 0x0};
#endif
#if defined(FLASH_UF2) && FLASH_UF2
ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
#endif
void board_init_console(void)
{
#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
console_config_t cfg;
/* uart needs to configure pin function before enabling clock, otherwise the level change of
uart rx pin when configuring pin function will cause a wrong data to be received.
And a uart rx dma request will be generated by default uart fifo dma trigger level. */
init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
cfg.type = BOARD_CONSOLE_TYPE;
cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE;
cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
if (status_success != console_init(&cfg)) {
/* failed to initialize debug console */
while (1) {
}
}
#else
while (1) {
}
#endif
#endif
}
void board_print_clock_freq(void)
{
printf("==============================\n");
printf(" %s clock summary\n", BOARD_NAME);
printf("==============================\n");
printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0));
printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1));
printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2));
printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc));
printf("==============================\n");
}
void board_init_uart(UART_Type *ptr)
{
/* configure uart's pin before opening uart's clock */
init_uart_pins(ptr);
board_init_uart_clock(ptr);
}
void board_print_banner(void)
{
const uint8_t banner[] = {"\n\
----------------------------------------------------------------------\n\
$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
----------------------------------------------------------------------\n"};
#ifdef SDK_VERSION_STRING
printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
#endif
printf("%s", banner);
}
static void board_turnoff_rgb_led(void)
{
uint8_t port_pin18_status;
uint8_t port_pin19_status;
uint8_t port_pin20_status;
uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18;
HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19;
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20;
HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl;
HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl;
HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl;
port_pin18_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 18);
port_pin19_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 19);
port_pin20_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 20);
invert_led_level = false;
/**
* hpm board evkmini Rev. B led light modification, resulting in two versions of rgb led processing different
*
*/
if ((port_pin18_status & port_pin19_status & port_pin20_status) == 0) {
/* Mini Rev B */
invert_led_level = true;
pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0);
HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl;
HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl;
HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl;
}
}
uint8_t board_get_led_pwm_off_level(void)
{
if (invert_led_level) {
return BOARD_LED_ON_LEVEL;
} else {
return BOARD_LED_OFF_LEVEL;
}
}
uint8_t board_get_led_gpio_off_level(void)
{
if (invert_led_level) {
return BOARD_LED_ON_LEVEL;
} else {
return BOARD_LED_OFF_LEVEL;
}
}
void board_ungate_mchtmr_at_lp_mode(void)
{
/* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
}
void board_init(void)
{
board_turnoff_rgb_led();
board_init_clock();
board_init_console();
board_init_pmp();
#if BOARD_SHOW_CLOCK
board_print_clock_freq();
#endif
#if BOARD_SHOW_BANNER
board_print_banner();
#endif
}
void board_init_core1(void)
{
clock_update_core_clock();
board_init_console();
board_init_pmp();
}
void board_init_sdram_pins(void)
{
init_femc_pins();
}
uint32_t board_init_femc_clock(void)
{
clock_add_to_group(clock_femc, 0);
clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */
return clock_get_frequency(clock_femc);
}
uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz);
#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13
static void set_reset_pin_level_tm070rdh13(uint8_t level)
{
gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, level);
}
static void set_backlight_tm070rdh13(uint16_t percent)
{
gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, percent > 0 ? 1 : 0);
}
void board_init_lcd_rgb_tm070rdh13(void)
{
init_lcd_pins(BOARD_LCD_BASE);
gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN);
gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN);
hpm_panel_hw_interface_t hw_if = {0};
hpm_panel_t *panel = hpm_panel_find_device_default();
const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel);
uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_display, timing->pixel_clock_khz);
hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13;
hw_if.set_backlight = set_backlight_tm070rdh13;
hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz;
hpm_panel_register_interface(panel, &hw_if);
printf("name: %s, lcdc_clk: %ukhz\n",
hpm_panel_get_name(panel),
lcdc_pixel_clk_khz);
hpm_panel_reset(panel);
hpm_panel_init(panel);
hpm_panel_power_on(panel);
}
#endif
#ifdef CONFIG_HPM_PANEL
uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz)
{
clock_add_to_group(clock_name, 0);
uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000;
uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz;
clock_set_source_divider(clock_name, clk_src_pll4_clk0, div);
return clock_get_frequency(clock_name) / 1000;
}
void board_lcd_backlight(bool is_on)
{
hpm_panel_t *panel = hpm_panel_find_device_default();
hpm_panel_set_backlight(panel, is_on == true ? 100 : 0);
}
void board_init_lcd(void)
{
#ifdef CONFIG_PANEL_RGB_TM070RDH13
board_init_lcd_rgb_tm070rdh13();
#endif
}
/*
* Fix Errata E00039
*
* The vpw in hpm67 soc is invalid, but actual timing of vpw is equal to hpw.
* So we need to fix the vpw to make it equal to hpw.
* The vpw is fixed by compensating the back porch, we need keep to total time of xsync and back porch unchanged.
*/
void board_lcdc_vpw_fix(lcdc_config_t *config)
{
uint32_t hpw = config->hsync.pulse_width;
uint32_t vpw = config->vsync.pulse_width;
uint32_t diff;
if (vpw < hpw) {
diff = hpw - vpw;
config->hsync.pulse_width = vpw;
config->hsync.back_porch_pulse += diff;
} else if (hpw < vpw) {
diff = vpw - hpw;
config->vsync.back_porch_pulse += diff;
}
}
void board_panel_para_to_lcdc(lcdc_config_t *config)
{
const hpm_panel_timing_t *timing;
hpm_panel_t *panel = hpm_panel_find_device_default();
timing = hpm_panel_get_timing(panel);
config->resolution_x = timing->hactive;
config->resolution_y = timing->vactive;
config->hsync.pulse_width = timing->hsync_len;
config->hsync.back_porch_pulse = timing->hback_porch;
config->hsync.front_porch_pulse = timing->hfront_porch;
config->vsync.pulse_width = timing->vsync_len;
config->vsync.back_porch_pulse = timing->vback_porch;
config->vsync.front_porch_pulse = timing->vfront_porch;
config->control.invert_hsync = timing->hsync_pol;
config->control.invert_vsync = timing->vsync_pol;
config->control.invert_href = timing->de_pol;
config->control.invert_pixel_data = timing->pixel_data_pol;
config->control.invert_pixel_clock = timing->pixel_clk_pol;
board_lcdc_vpw_fix(config);
}
#endif
void board_delay_ms(uint32_t ms)
{
clock_cpu_delay_ms(ms);
}
void board_delay_us(uint32_t us)
{
clock_cpu_delay_us(us);
}
#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
static board_timer_cb timer_cb;
SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr)
void board_timer_isr(void)
{
if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
timer_cb();
}
}
void board_timer_create(uint32_t ms, board_timer_cb cb)
{
uint32_t gptmr_freq;
gptmr_channel_config_t config;
timer_cb = cb;
gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
config.reload = gptmr_freq / 1000 * ms;
gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
}
#endif
void board_i2c_bus_clear(I2C_Type *ptr)
{
init_i2c_pins_as_gpio(ptr);
if (ptr == BOARD_CAP_I2C_BASE) {
gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN);
gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) {
printf("CLK is low, please power cycle the board\n");
while (1) {
}
}
if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) {
printf("SDA is low, try to issue I2C bus clear\n");
} else {
printf("I2C bus is ready\n");
return;
}
gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
for (uint8_t i = 0; i < 3; i++) {
for (uint32_t j = 0; j < 9; j++) {
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1);
board_delay_ms(10);
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0);
board_delay_ms(10);
}
board_delay_ms(100);
}
printf("I2C bus is cleared\n");
}
}
uint32_t board_init_i2c_clock(I2C_Type *ptr)
{
uint32_t freq = 0;
if (ptr == HPM_I2C0) {
clock_add_to_group(clock_i2c0, 0);
freq = clock_get_frequency(clock_i2c0);
} else if (ptr == HPM_I2C1) {
clock_add_to_group(clock_i2c1, 0);
freq = clock_get_frequency(clock_i2c1);
} else if (ptr == HPM_I2C2) {
clock_add_to_group(clock_i2c2, 0);
freq = clock_get_frequency(clock_i2c2);
} else if (ptr == HPM_I2C3) {
clock_add_to_group(clock_i2c3, 0);
freq = clock_get_frequency(clock_i2c3);
} else {
;
}
return freq;
}
void board_init_i2c(I2C_Type *ptr)
{
i2c_config_t config;
hpm_stat_t stat;
uint32_t freq;
freq = board_init_i2c_clock(ptr);
board_i2c_bus_clear(ptr);
init_i2c_pins(ptr);
config.i2c_mode = i2c_mode_normal;
config.is_10bit_addressing = false;
stat = i2c_init_master(ptr, freq, &config);
if (stat != status_success) {
printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
while (1) {
}
}
}
uint32_t board_init_uart_clock(UART_Type *ptr)
{
uint32_t freq = 0U;
if (ptr == HPM_UART0) {
clock_add_to_group(clock_uart0, 0);
freq = clock_get_frequency(clock_uart0);
} else if (ptr == HPM_UART6) {
clock_add_to_group(clock_uart6, 0);
freq = clock_get_frequency(clock_uart6);
} else if (ptr == HPM_UART7) {
clock_add_to_group(clock_uart7, 0);
freq = clock_get_frequency(clock_uart7);
} else if (ptr == HPM_UART13) {
clock_add_to_group(clock_uart13, 0);
freq = clock_get_frequency(clock_uart13);
} else if (ptr == HPM_UART14) {
clock_add_to_group(clock_uart14, 0);
freq = clock_get_frequency(clock_uart14);
} else {
/* Not supported */
}
return freq;
}
uint32_t board_init_spi_clock(SPI_Type *ptr)
{
if (ptr == HPM_SPI2) {
clock_add_to_group(clock_spi2, 0);
return clock_get_frequency(clock_spi2);
} else {
return 0;
}
}
void board_init_cap_touch(void)
{
init_cap_pins();
gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0);
gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
board_delay_ms(1);
gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
board_delay_ms(1);
gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1);
board_delay_ms(55);
gpio_set_pin_input(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN);
board_init_i2c(BOARD_CAP_I2C_BASE);
}
void board_init_gpio_pins(void)
{
init_gpio_pins();
}
void board_init_spi_pins(SPI_Type *ptr)
{
init_spi_pins(ptr);
}
void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
{
init_spi_pins_with_gpio_as_cs(ptr);
gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
}
void board_write_spi_cs(uint32_t pin, uint8_t state)
{
gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
}
void board_init_led_pins(void)
{
board_turnoff_rgb_led();
init_led_pins_as_gpio();
gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level());
gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level());
gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level());
}
void board_led_toggle(void)
{
static uint8_t i;
if (!invert_led_level) {
/* hpm6750 Mini Rev A led configure*/
gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN);
} else {
/* hpm6750 Mini Rev B led configure*/
gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, ((1 << i)) << BOARD_G_GPIO_PIN);
}
i++;
i = i % 3;
}
void board_led_write(uint8_t state)
{
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
}
void board_init_cam_pins(void)
{
init_cam_pins(HPM_CAM0);
}
void board_init_usb(USB_Type *ptr)
{
if (ptr == HPM_USB0) {
init_usb_pins(ptr);
clock_add_to_group(clock_usb0, 0);
}
}
void board_init_pmp(void)
{
uint32_t start_addr;
uint32_t end_addr;
uint32_t length;
pmp_entry_t pmp_entry[16];
uint8_t index = 0;
/* Init noncachable memory */
extern uint32_t __noncacheable_start__[];
extern uint32_t __noncacheable_end__[];
start_addr = (uint32_t) __noncacheable_start__;
end_addr = (uint32_t) __noncacheable_end__;
length = end_addr - start_addr;
if (length > 0) {
/* Ensure the address and the length are power of 2 aligned */
assert((length & (length - 1U)) == 0U);
assert((start_addr & (length - 1U)) == 0U);
pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
index++;
}
/* Init share memory */
extern uint32_t __share_mem_start__[];
extern uint32_t __share_mem_end__[];
start_addr = (uint32_t)__share_mem_start__;
end_addr = (uint32_t)__share_mem_end__;
length = end_addr - start_addr;
if (length > 0) {
/* Ensure the address and the length are power of 2 aligned */
assert((length & (length - 1U)) == 0U);
assert((start_addr & (length - 1U)) == 0U);
pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
index++;
}
pmp_config(&pmp_entry[0], index);
}
void board_init_clock(void)
{
uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
/* Configure the External OSC ramp-up time: ~9ms */
pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U);
/* Select clock setting preset1 */
sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
}
/* Add clocks to group 0 */
clock_add_to_group(clock_cpu0, 0);
clock_add_to_group(clock_mchtmr0, 0);
clock_add_to_group(clock_axi0, 0);
clock_add_to_group(clock_axi1, 0);
clock_add_to_group(clock_axi2, 0);
clock_add_to_group(clock_ahb, 0);
clock_add_to_group(clock_xdma, 0);
clock_add_to_group(clock_hdma, 0);
clock_add_to_group(clock_xpi0, 0);
clock_add_to_group(clock_xpi1, 0);
clock_add_to_group(clock_ram0, 0);
clock_add_to_group(clock_ram1, 0);
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_lmm1, 0);
clock_add_to_group(clock_gpio, 0);
clock_add_to_group(clock_mot0, 0);
clock_add_to_group(clock_mot1, 0);
clock_add_to_group(clock_mot2, 0);
clock_add_to_group(clock_mot3, 0);
clock_add_to_group(clock_synt, 0);
clock_add_to_group(clock_ptpc, 0);
/* Connect Group0 to CPU0 */
clock_connect_group_to_cpu(0, 0);
/* Add clocks to Group1 */
clock_add_to_group(clock_cpu1, 1);
clock_add_to_group(clock_mchtmr1, 1);
/* Connect Group1 to CPU1 */
clock_connect_group_to_cpu(1, 1);
/* Bump up DCDC voltage to 1275mv */
pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG);
if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ);
while (1) {
}
}
clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
clock_update_core_clock();
clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/
clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
}
uint32_t board_init_cam_clock(CAM_Type *ptr)
{
uint32_t freq = 0;
if (ptr == HPM_CAM0) {
/* Configure camera clock to 24MHz */
clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U);
clock_add_to_group(clock_camera0, 0);
freq = clock_get_frequency(clock_camera0);
} else if (ptr == HPM_CAM1) {
/* Configure camera clock to 24MHz */
clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U);
clock_add_to_group(clock_camera1, 0);
freq = clock_get_frequency(clock_camera1);
} else {
/* Invalid camera instance */
}
return freq;
}
uint32_t board_init_dao_clock(void)
{
clock_add_to_group(clock_dao, 0);
board_config_i2s_clock(DAO_I2S, 48000);
return clock_get_frequency(clock_dao);
}
uint32_t board_init_pdm_clock(void)
{
clock_add_to_group(clock_pdm, 0);
board_config_i2s_clock(PDM_I2S, 16000);
return clock_get_frequency(clock_pdm);
}
hpm_stat_t board_set_audio_pll_clock(uint32_t freq)
{
return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */
}
void board_init_i2s_pins(I2S_Type *ptr)
{
init_i2s_pins(ptr);
}
uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate)
{
uint32_t freq = 0;
if (ptr == HPM_I2S0) {
clock_add_to_group(clock_i2s0, 0);
if ((sample_rate % 22050) == 0) {
clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */
} else {
clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */
}
clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0);
freq = clock_get_frequency(clock_i2s0);
} else if (ptr == HPM_I2S1) {
clock_add_to_group(clock_i2s1, 0);
if ((sample_rate % 22050) == 0) {
clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */
} else {
clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */
}
clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1);
freq = clock_get_frequency(clock_i2s1);
} else {
;
}
return freq;
}
void board_init_adc12_pins(void)
{
init_adc12_pins();
}
void board_init_adc16_pins(void)
{
init_adc16_pins();
}
uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)
{
uint32_t freq = 0;
if (ptr == (void *)HPM_ADC0) {
if (clk_src_bus) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
} else {
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
}
clock_add_to_group(clock_adc0, 0);
freq = clock_get_frequency(clock_adc0);
} else if (ptr == (void *)HPM_ADC1) {
if (clk_src_bus) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
} else {
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U);
}
clock_add_to_group(clock_adc1, 0);
freq = clock_get_frequency(clock_adc1);
} else if (ptr == (void *)HPM_ADC2) {
if (clk_src_bus) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
} else {
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U);
}
clock_add_to_group(clock_adc2, 0);
freq = clock_get_frequency(clock_adc2);
} else if (ptr == (void *)HPM_ADC3) {
if (clk_src_bus) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc3, clk_adc_src_ahb0);
} else {
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
clock_set_adc_source(clock_adc3, clk_adc_src_ana2);
clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U);
}
clock_add_to_group(clock_adc3, 0);
freq = clock_get_frequency(clock_adc3);
}
return freq;
}
void board_init_acmp_pins(void)
{
init_acmp_pins();
}
void board_init_acmp_clock(ACMP_Type *ptr)
{
(void)ptr;
clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
}
void board_init_can(CAN_Type *ptr)
{
init_can_pins(ptr);
}
uint32_t board_init_can_clock(CAN_Type *ptr)
{
uint32_t freq = 0;
if (ptr == HPM_CAN0) {
/* Set the CAN0 peripheral clock to 80MHz */
clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5);
clock_add_to_group(clock_can0, 0);
freq = clock_get_frequency(clock_can0);
} else if (ptr == HPM_CAN1) {
/* Set the CAN1 peripheral clock to 80MHz */
clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5);
clock_add_to_group(clock_can1, 0);
freq = clock_get_frequency(clock_can1);
} else if (ptr == HPM_CAN2) {
/* Set the CAN2 peripheral clock to 80MHz */
clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5);
clock_add_to_group(clock_can2, 0);
freq = clock_get_frequency(clock_can2);
} else if (ptr == HPM_CAN3) {
/* Set the CAN3 peripheral clock to 80MHz */
clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5);
clock_add_to_group(clock_can3, 0);
freq = clock_get_frequency(clock_can3);
} else {
/* Invalid CAN instance */
}
return freq;
}
#ifdef INIT_EXT_RAM_FOR_DATA
/*
* this function will be called during startup to initialize external memory for data use
*/
void _init_ext_ram(void)
{
uint32_t femc_clk_in_hz;
femc_config_t config = {0};
femc_sdram_config_t sdram_config = {0};
board_init_sdram_pins();
femc_clk_in_hz = board_init_femc_clock();
femc_default_config(HPM_FEMC, &config);
femc_init(HPM_FEMC, &config);
femc_get_typical_sdram_config(HPM_FEMC, &sdram_config);
sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
sdram_config.prescaler = 0x3;
sdram_config.burst_len_in_byte = 8;
sdram_config.auto_refresh_count_in_one_burst = 1;
sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS;
sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */
sdram_config.refresh_recover_in_ns = 60; /* Trc */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_act_in_ns = 12; /* Trrd */
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */
sdram_config.cs = BOARD_SDRAM_CS;
sdram_config.base_address = BOARD_SDRAM_ADDRESS;
sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
sdram_config.delay_cell_disable = true;
sdram_config.delay_cell_value = 0;
femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
}
#endif
uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse)
{
uint32_t actual_freq = 0;
do {
clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1;
clock_add_to_group(sdxc_clk, 0);
sdxc_enable_inverse_clock(ptr, false);
sdxc_enable_sd_clock(ptr, false);
/* Configure the clock below 400KHz for the identification state */
if (freq <= 400000UL) {
clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63);
}
/* configure the clock to 24MHz for the SDR12/Default speed */
else if (freq <= 26000000UL) {
clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
}
/* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
else if (freq <= 52000000UL) {
clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8);
}
/* Configure the clock to 100MHz for the SDR50 */
else if (freq <= 100000000UL) {
clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4);
}
/* Configure the clock to 166MHz for SDR104/HS200/HS400 */
else if (freq <= 208000000UL) {
clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2);
}
/* For other unsupported clock ranges, configure the clock to 24MHz */
else {
clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
}
if (need_inverse) {
sdxc_enable_inverse_clock(ptr, true);
}
hpm_stat_t status = clock_wait_source_stable(sdxc_clk);
if (status != status_success) {
break;
}
sdxc_enable_sd_clock(ptr, true);
actual_freq = clock_get_frequency(sdxc_clk);
} while (false);
return actual_freq;
}
static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index)
{
pwm_cmp_config_t cmp_config = {0};
pwm_output_channel_t ch_config = {0};
pwm_stop_counter(ptr);
pwm_get_default_cmp_config(ptr, &cmp_config);
pwm_get_default_output_channel_config(ptr, &ch_config);
pwm_set_reload(ptr, 0, 0xF);
pwm_set_start_count(ptr, 0, 0);
cmp_config.mode = pwm_cmp_mode_output_compare;
cmp_config.cmp = 0x10;
cmp_config.update_trigger = pwm_shadow_register_update_on_modify;
pwm_config_cmp(ptr, cmp_index, &cmp_config);
ch_config.cmp_start_index = cmp_index;
ch_config.cmp_end_index = cmp_index;
ch_config.invert_output = !board_get_led_pwm_off_level();
pwm_config_output_channel(ptr, pin, &ch_config);
}
void board_init_rgb_pwm_pins(void)
{
board_turnoff_rgb_led();
set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP);
set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP);
set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP);
init_led_pins_as_pwm();
}
void board_disable_output_rgb_led(uint8_t color)
{
switch (color) {
case BOARD_RGB_RED:
pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
break;
case BOARD_RGB_GREEN:
pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
break;
case BOARD_RGB_BLUE:
pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
break;
default:
while (1) {
;
}
}
}
void board_enable_output_rgb_led(uint8_t color)
{
switch (color) {
case BOARD_RGB_RED:
pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
break;
case BOARD_RGB_GREEN:
pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
break;
case BOARD_RGB_BLUE:
pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
break;
default:
while (1) {
;
}
}
}
void board_init_beep_pwm_pins(void)
{
init_beep_pwm_pins();
}
hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
{
if (ptr == HPM_ENET0) {
clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1);
clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */
} else if (ptr == HPM_ENET1) {
clock_add_to_group(clock_ptp1, BOARD_RUNNING_CORE & 0x1);
clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */
} else {
return status_invalid_argument;
}
return status_success;
}
hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
{
clock_name_t eth_clk = (ptr == HPM_ENET0) ? clock_eth0 : clock_eth1;
/* Configure Enet clock to output reference clock */
clock_add_to_group(eth_clk, BOARD_RUNNING_CORE & 0x1);
if (internal) {
/* set pll output frequency at 1GHz */
if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) {
/* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 */
pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4);
/* set eth clock frequency at 50MHz for enet0 */
clock_set_source_divider(eth_clk, clk_src_pll2_clk1, 5);
} else {
return status_fail;
}
}
enet_rmii_enable_clock(ptr, internal);
return status_success;
}
hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
{
init_enet_pins(ptr);
if (ptr == HPM_ENET1) {
gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0);
} else {
return status_invalid_argument;
}
return status_success;
}
hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
{
if (ptr == HPM_ENET1) {
gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0);
board_delay_ms(1);
gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1);
} else {
return status_invalid_argument;
}
return status_success;
}
uint8_t board_get_enet_dma_pbl(ENET_Type *ptr)
{
(void) ptr;
return enet_pbl_32;
}
hpm_stat_t board_enable_enet_irq(ENET_Type *ptr)
{
if (ptr == HPM_ENET0) {
intc_m_enable_irq(IRQn_ENET0);
} else if (ptr == HPM_ENET1) {
intc_m_enable_irq(IRQn_ENET1);
} else {
return status_invalid_argument;
}
return status_success;
}
hpm_stat_t board_disable_enet_irq(ENET_Type *ptr)
{
(void) ptr;
return status_success;
}
void board_init_enet_pps_pins(ENET_Type *ptr)
{
(void) ptr;
init_enet_pps_pins();
}
void board_init_enet_pps_capture_pins(ENET_Type *ptr)
{
(void) ptr;
init_enet_pps_capture_pins();
}
void board_init_dao_pins(void)
{
init_dao_pins();
}
void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
{
init_gptmr_channel_pin(ptr, channel, as_comp);
}
void board_init_clk_ref_pin(void)
{
init_clk_ref_pin();
}
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
{
uint32_t freq = 0U;
if (ptr == HPM_GPTMR0) {
clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr0);
} else if (ptr == HPM_GPTMR1) {
clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr1);
} else if (ptr == HPM_GPTMR2) {
clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr2);
} else if (ptr == HPM_GPTMR3) {
clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr3);
} else if (ptr == HPM_GPTMR4) {
clock_add_to_group(clock_gptmr4, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr4);
} else if (ptr == HPM_GPTMR5) {
clock_add_to_group(clock_gptmr5, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr5);
} else if (ptr == HPM_GPTMR6) {
clock_add_to_group(clock_gptmr6, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr6);
} else if (ptr == HPM_GPTMR7) {
clock_add_to_group(clock_gptmr7, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr7);
} else if (ptr == HPM_PTMR) {
clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_ptmr);
} else {
/* Not supported */
}
return freq;
}
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