`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/16 14:58:00
// Design Name: 
// Module Name: BranchUnit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "Parameters.v"
import Params::*;

module BranchUnit(
input logic [31:0] Reg1,               //第一个源操作数
input logic [31:0] Reg2,               //第二个源操作数
input BType BrType,              //条件分支指令类型
output logic BranchE                   //是否跳转
    );
always_comb 
begin
    case(BrType)
        BEQ:if(Reg1==Reg2)
                 BranchE=1;
             else
                 BranchE=0;
        BNE:if(Reg1!=Reg2)
                 BranchE=1;
             else
                 BranchE=0;
        BLT:if($signed(Reg1)<$signed(Reg1))            //有符号数比较
                 BranchE=1;
             else
                 BranchE=0;
        BLTU:if(Reg1<Reg2)
                 BranchE=1;
              else
                 BranchE=0;
        BGE:if($signed(Reg1)>=$signed(Reg2))          //有符号数比较
                 BranchE=1;
             else
                 BranchE=0;
        BGEU:if(Reg1>=Reg2)
                 BranchE=1;
              else
                 BranchE=0;
        default:BranchE=0;
    endcase
end
endmodule