Digiblock 标签 - Gitee.com

v1.0

aee3bed

2021-09-30 11:08

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v0.30

2703601

2020-03-09 21:44

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v0.23

Added generic circuits and simplified the integration of FPGA boards.

- Added generic circuits. Now it is possible to parameterize a sub circuit.
  Allows e.g. the creation of a barrel-shifter with selectable bit width.
- Circuit analyser is now able to analyse the built-in counters.
- Simplified the integration of FPGA boards.
  Board integration is now possible without creating Java code or
  even recompiling. See the BASYS3.config in examples/hdl as an example.
- Improved the label creation in the model analyzer.
- Improved performance of the boolean equation minimizer.
- Hex reader/writer supports RLE encoding like Logisim does.
- Added Spanish translation. Special thanks to Ángel Millán who provided
  the translation.
- Added a simple interactive beginners tutorial.
- Added a statistics dialog which shows the number of used components.
- Added scrollbars.
- Multiple break components are allowed.
- The fsm dialog loads the correct fsm if a circuit is open which
  is based on that fsm.
- If a VHDL defined component is used, ghdl now uses VHDL-2008.
- Added "Warren’s Crazy Small CPU" designed by Warren Toomey as a
  74xx circuit example.
- Fixed an issue in the "RAM, Chip select" component which was not fully
  asynchronous.
- Fixed swapped IC numbers 7447 and 7448.

9eccfa6

2019-08-23 19:03

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v0.22

71be07a

2019-04-01 15:35

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v0.21

eea5b03

2018-12-10 17:43

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v0.20

Added a new more flexible shape for embedded circuits.

- Improved zooming and navigating in the measurement graph.
- Added multi pole double-throw relays.
- Added EEPROM with separate ports for reading and writing.
- Added a hi-color mode (5 bits per color channel) to the graphic RAM.
- The external assembly IDE is able to preload also RAMs with executable code.
  The register representing the program counter must be marked as such.
- Allows the pre-loading of program memory if a RAM is used as such, via the
  circuit settings.
- Added a new more flexible shape for embedded circuits.
- Breaking changes:
  - If you have build a processor and are using the simulators tcp interface,
    you have to flag the register which represents the program counter as such.
  - If you have used the 74xx library components with the schematic shape, you
    have to reselect the shape.
  - In your own DIL circuits you have to reselect the DIL shape in the
    circuit settings. If you have build a custom shape, you also have to
    reselect it.

9f04225

2018-09-03 22:32

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v0.19

Added export to Verilog

- Added a tabbed pane to the attributes dialog to make it more beginner friendly.
- Added support for asynchronous sequential circuits such as the Muller-pipeline.
  Take a look at the new asynchronous examples for illustration.
- Added export to Verilog. Special thanks to Ivan de Jesus Deras Tabora, who has
  implemented the Verilog code generator and all the necessary Verilog templates!
- All examples are translated to english.
- A "test all" function has been added to start all tests in all circuits in
  the current folder.
- Very basic support for custom shapes added.
  You must manually edit the *.dig file to add a custom shape to a circuit, so
  this is only an option for advanced users.
- It is possible to use the 74xx chips with a more schematic shape, making it
  easier to build a circuit.
- Breaking changes:
  - Added an enable input to the terminal component.
  - Added a clock input to the keyboard component.
  - In your own DIL chips, you must correct the width attribute.
    The new value can be calculated as follows: new = (old*2)-1
- Bug fixes
  - Fixed a bug in the VHDL export concerning an invalid optimization of a
    std_logic_vector access.

3e03dd6

2018-06-14 14:56

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v0.18

Significant improvement of the generated vhdl code.

- Significant improvement in the quality of the generated vhdl code.
- Its possible to define the behaviour of a component using vhdl.
  The vhdl simulator ghdl needs to be installed to use a vhdl defined component.
- Removed the high-z restrictions from the splitter.
  Now a bus can have different high z states for the different lines on the bus.
- Added new text formatting engine which supports overline, super- and subscript.
  Try "~Q_{n+1}^1" as an output label.
- When a circuit containing a ROM/EEPROM is embedded multiple times, it is now
  possible to define different ROM/EEPROM contents in each embedded instance.
- It's possible to test circuits with a high-z input which can act as an output.
- An embedded circuit that is used in the library and whose name ends with
  '-inc.dig' is shown neither in the component menu nor in the tree view.
- Added a improved counter with preset.
- Added a monoflop. Needs a clock in the circuit in order to work.
- Added a 16 segment display.
- Added a polarity aware LED.
- Added a DIP switch.
- Added a simple bidirectional splitter.
- Added ICs 74181, 74779, 7440 and 7428

d750e4e

2018-04-02 17:13

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v0.17

3649cc7

2018-02-20 04:15

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v0.16

Many small changes and improvements.

- RAM components and EEPROM now allow an input invert configuration.
- Measurement values dialog is also able to modify the values. This allows to modify
  the content of registers and flip-flops in a running simulation.
- Now you can open the measurement value table and graph in a running simulation.
- Added a bit extender component to extend signed values.
- Added a simple unclocked RS flip-flop.
- Added a bit selector component.
- Added a dual ported RAM component.
- Added a priority encoder component.
- Added tooltips showing the actual value of wires.
- Added a shortcut S to split a single wire into two wires.
- Added selectable number format to inputs and outputs.
- Now you can click in the k-map to modify the truth table.
- Improved performance through more efficient decoupling of the GUI thread and the simulation thread.
- Bug fixes
  - Fixed a bug in the RAMSinglePortSel component: Write was not edge-triggered on WE. Now it is.
  - Fixed a bug in the barrel shifter and adder if 32 bits or more where used.
  - It was not possible to use constants with 32 bits or more. Now it is.
  - Fixed a bug that caused the exported VHDL code not to work if a signal was connected
    to multiple outputs.
  - Fixed "concurrent modification exception" if input value dialog is opened.
- Breaking changes:
  - Counter modified from a asynchronous clear to a synchronous clear.

04c62b6

2018-01-02 22:55

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v0.15

Support of custom, java implemented components

- Added the possibility to use custom, java implemented components in Digital.
- Added an EEPROM which behaves like a memory that can be written and whose content
  is non-volatile.
- Added the possibility to map keyboard keys to model buttons.
- Some small usability improvements:
  - Added a grid to the main panel.
  - Replaced shortcut 'B' with a more general attribute editing dialog (select multiple
    components and click right).
  - Added some new shortcuts (CTRL-N, CTRL-O, CTRL-A, CTRL-D).
  - Added a spinner to the input value edit dialog.
- Bug fixes
  - fixed bugs in some 74xx circuits (74160, 74161, 74162 and 74238)
  - fixed a bug in the remote interface "run to break" method.
  - fixed an error in VHDL export if comparator is used in "signed mode"
  - fixed a Windows specific bug in the speed test GUI
  - fixed a bug which causes a freezing when a file is stored in folder which contains
    a large number of sub folders and files.
- Breaking changes:
  - Removed the address bits settings from the graphic RAM. The width is now
    determined by the width and the height of the screen.

7f987f2

2017-10-30 16:55

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v0.14

Added KV maps and VHDL export

- Added visualization of KV maps (thanks to roy77)
- Added VHDL export
  (Not yet complete, but the example processor is running on a FPGA.)
- Type of pin numbers changed from int to string to allow FPGA pin names like "U16".
- Added support for BASYS3-Board (*.xdc constrains file is written and the mixed mode
  clock manager (MMCM) is used if clock frequency exceeds 37kHz)
- Added shortcut 'B' which sets the number of data bits in all selected components.
- Breaking changes:
  - To generalize the VHDL export, an XML entity in the *.dig files had to be renamed.
    As a consequence of that the address bits settings in RAMs and ROMs
    are lost. To fix that, reset the number of address bits.
  - Added an enable input to the counter component. If you had used the counter in the
    past you have to set the en input to 1. The function of the overflow output also
    has changed (see tooltip) and now allows the cascading of counters.
  - XOR now can have more than two inputs. If you had used the XOR gate with inverted
    inputs, you have to reselect the inputs to invert.
- Some minor bug fixes.

725b590

2017-08-31 22:36

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v0.13

Introduced a library of sub circuits

- Introduced a library of sub circuits which are available in every circuit.
  So far, the library contains only the 74xx circuits.
- Added a barrel shifter (thanks to roy77)
- some improvements concerning error messages:
  - In case of oscillations almost all affected components are shown.
  - If an error occurs, the name of the affected circuit file is shown.
  - If an error occurs, the causing sub circuit is highlighted.
  - A warning message shows up if a circuit with unnamed inputs is analysed.
  - A warning message shows up if a circuit with missing pin numbers is exported to a
    hardware-related file.
- An input can have "high z" value as its default value.
  CAUTION: All inputs have lost their default values! If you have build a circuit that
           contains test cases that depend on a non-null default value, this tests
           will fail. To resolve this issue, reset the default value.
- Added an enable input to the T flip-flop
  CAUTION: By default this input is activated now. In circuits which used the T flip-flop
           in the past, the new input needs to be disabled.
- Unidirectional FETs are added to overcome certain CMOS issues.
- Added zooming to measurement graphs.
- Test results can be displayed as measurement graphs.
- The Text component is able to show multiple lines.
- Comments are allowed in hex files.
- Some minor bug fixes

37ece25

2017-07-25 13:50

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v0.12.1

93a576c

2017-06-06 02:00

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v0.12

a3eda62

2017-06-02 21:44

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v0.11.1