@robbietoo
robbietoo 暂无简介
用于显示、修改寄存器的每个Bit。
verilator 安装包
A Verilator-based demo.
Verilator open-source SystemVerilog simulator and lint system
Rocket Chip Generator
Icarus Verilog
UVM 1.2 port to Python
Digital Design with Chisel
Functional verification project for the CORE-V family of RISC-V cores.
Chisel 3: A Modern Hardware Design Language
Generator Bootcamp Material: Learn Chisel the Right Way
RISC-V SoC designed by students in UCAS
Open-source high-performance RISC-V processor
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python