#include "reginfo.h"
#include "chipid.h"
#include "hal/hisi/hal_hisi.h"
#include "tools.h"

#include <assert.h>
#include <ctype.h>
#include <getopt.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>

typedef const struct {
    uint32_t address;
    const char *funcs[];
} muxctrl_reg_t;

#define MUXCTRL(name, addr, ...)                                               \
    static muxctrl_reg_t name = {addr, {__VA_ARGS__, 0}};

MUXCTRL(CV100_0, 0x200f0000, "GPIO1_0", "SHUTTER_TRIG")
MUXCTRL(CV100_1, 0x200f0004, "GPIO1_1", "SDIO_CCLK_OUT")
MUXCTRL(CV100_2, 0x200f0008, "GPIO1_2", "SENSOR_CLK")
MUXCTRL(CV100_3, 0x200f000c, "GPIO1_4", "SPI0_SCLK")
MUXCTRL(CV100_4, 0x200f0010, "GPIO1_5", "SPI0_SDO")
MUXCTRL(CV100_5, 0x200f0014, "GPIO1_6", "SPI0_SDI")
MUXCTRL(CV100_6, 0x200f0018, "GPIO2_0", "I2C_SDA")
MUXCTRL(CV100_7, 0x200f001c, "GPIO2_1", "I2C_SCL")
MUXCTRL(CV100_8, 0x200f0020, "GPIO2_2", "UART1_RTSN")
MUXCTRL(CV100_9, 0x200f0024, "GPIO2_3", "UART1_RXD")
MUXCTRL(CV100_10, 0x200f0028, "GPIO2_4", "UART1_CTSN")
MUXCTRL(CV100_11, 0x200f002c, "GPIO2_5", "UART1_TXD")
MUXCTRL(CV100_12, 0x200f0030, "GPIO3_0", "MII_CRS", "VOU1120_DATA10")
MUXCTRL(CV100_13, 0x200f0034, "GPIO3_1", "MII_COL", "VOU1120_DATA9")
MUXCTRL(CV100_14, 0x200f0038, "GPIO4_3", "MII_RXD3", "VOU1120_DATA15")
MUXCTRL(CV100_15, 0x200f003c, "GPIO4_2", "MII_RXD2", "VOU1120_DATA11")
MUXCTRL(CV100_16, 0x200f0040, "GPIO4_1", "MII_RXD1", "VOU1120_DATA8")
MUXCTRL(CV100_17, 0x200f0044, "GPIO4_0", "MII_RXD0", "VOU1120_DATA12")
MUXCTRL(CV100_18, 0x200f0048, "GPIO4_7", "MII_TXD3", "VOU1120_DATA3")
MUXCTRL(CV100_19, 0x200f004c, "GPIO4_6", "MII_TXD2", "VOU1120_DATA13")
MUXCTRL(CV100_20, 0x200f0050, "GPIO4_5", "MII_TXD1", "VOU1120_DATA0")
MUXCTRL(CV100_21, 0x200f0054, "GPIO4_4", "MII_TXD0", "VOU1120_DATA4")
MUXCTRL(CV100_22, 0x200f0058, "GPIO3_2", "MII_RXCK", "VOU1120_CLK")
MUXCTRL(CV100_23, 0x200f005c, "GPIO3_3", "MII_TXCK", "VOU1120_DATA7",
        "RMII_CLK")
MUXCTRL(CV100_24, 0x200f0060, "GPIO3_4", "MII_RXDV", "VOU1120_DATA1")
MUXCTRL(CV100_25, 0x200f0064, "GPIO3_5", "MII_TXEN", "VOU1120_DATA5")
MUXCTRL(CV100_26, 0x200f0068, "GPIO2_6", "MII_TXER")
MUXCTRL(CV100_27, 0x200f006c, "GPIO2_7", "MII_RXER")
MUXCTRL(CV100_28, 0x200f0070, "GPIO1_3", "EPHY_CLK", "VOU1120_DATA2")
MUXCTRL(CV100_29, 0x200f0074, "GPIO3_6", "MDCK", "VOU1120_DATA6", "BOOT_SEL")
MUXCTRL(CV100_30, 0x200f0078, "GPIO3_7", "MDIO", "VOU1120_DATA14")
MUXCTRL(CV100_31, 0x200f007c, "GPIO1_7", "FLASH_TRIG")
MUXCTRL(CV100_32, 0x200f0080, "GPIO6_0", "SDIO_CARD_DETECT")
MUXCTRL(CV100_33, 0x200f0084, "GPIO6_1", "SDIO_CARD_POWER_EN")
MUXCTRL(CV100_34, 0x200f0088, "GPIO6_2", "SDIO_CWPR")
MUXCTRL(CV100_35, 0x200f008c, "GPIO6_3", "SDIO_CCMD")
MUXCTRL(CV100_36, 0x200f0090, "GPIO6_4", "SDIO_CDATA0", "CLK_TEST_OUT0",
        "CLK_TEST_OUT1", "CLK_TEST_OUT2", "CLK_TEST_OUT3")
MUXCTRL(CV100_37, 0x200f0094, "PLL_TEST_OUT0", "SDIO_CDATA1", "GPIO6_5",
        "PLL_TEST_OUT1", "PLL_TEST_OUT2", "PLL_TEST_OUT3", "RTC_TEST_CLK")
MUXCTRL(CV100_38, 0x200f0098, "GPIO6_6", "SDIO_CDATA2")
MUXCTRL(CV100_39, 0x200f009c, "GPIO6_7", "SDIO_CDATA3")
MUXCTRL(CV100_40, 0x200f00a0, "SFC_DIO", "GPIO7_0")
MUXCTRL(CV100_41, 0x200f00a4, "SFC_WP_IO2", "GPIO7_1")
MUXCTRL(CV100_42, 0x200f00a8, "SFC_CLK", "GPIO7_2", "SFC_ADDR_MODE")
MUXCTRL(CV100_43, 0x200f00ac, "SFC_DOI", "GPIO7_3")
MUXCTRL(CV100_44, 0x200f00b0, "SFC_HOLD_IO3", "GPIO7_4")
MUXCTRL(CV100_45, 0x200f00b4, "GPIO5_0", "USB_OVRCUR")
MUXCTRL(CV100_46, 0x200f00b8, "GPIO5_1", "USB_PWREN")
MUXCTRL(CV100_47, 0x200f00bc, "GPIO5_2", "PWM_OUT0")
MUXCTRL(CV100_48, 0x200f00c0, "GPIO5_3", "PWM_OUT1")
MUXCTRL(CV100_49, 0x200f00c4, "IR_IN", "GPIO7_5")
MUXCTRL(CV100_50, 0x200f00c8, "reserved", "GPIO9_0")
MUXCTRL(CV100_51, 0x200f00cc, "reserved", "GPIO9_1")
MUXCTRL(CV100_52, 0x200f00d0, "reserved", "GPIO9_2")
MUXCTRL(CV100_53, 0x200f00d4, "reserved", "GPIO9_3")
MUXCTRL(CV100_54, 0x200f00d8, "reserved", "GPIO9_4")
MUXCTRL(CV100_55, 0x200f00dc, "reserved", "GPIO9_5")
MUXCTRL(CV100_56, 0x200f00e0, "reserved", "GPIO9_6")
MUXCTRL(CV100_57, 0x200f00e4, "reserved", "GPIO9_7")
MUXCTRL(CV100_66, 0x200f0108, "GPIO7_6", "UART2_RXD")
MUXCTRL(CV100_67, 0x200f010c, "GPIO7_7", "UART2_TXD")
MUXCTRL(CV100_68, 0x200f0110, "GPIO5_4", "SPI1_SCLK")
MUXCTRL(CV100_69, 0x200f0114, "GPIO5_5", "SPI1_SDO")
MUXCTRL(CV100_70, 0x200f0118, "GPIO5_6", "SPI1_SDI")
MUXCTRL(CV100_71, 0x200f011c, "GPIO5_7", "SPI1_CSN")
MUXCTRL(CV100_72, 0x200f0120, "GPIO0_0", "JTAG_TRSTN", "TEMPER_DQ")
MUXCTRL(CV100_73, 0x200f0124, "GPIO0_1", "JTAG_TCK", "TEMPER_DQ")
MUXCTRL(CV100_74, 0x200f0128, "GPIO0_2", "JTAG_TMS", "TEMPER_DQ")
MUXCTRL(CV100_75, 0x200f012c, "GPIO0_3", "JTAG_TDO", "TEMPER_DQ")
MUXCTRL(CV100_76, 0x200f0130, "GPIO0_4", "JTAG_TDI", "TEMPER_DQ")
MUXCTRL(CV100_77, 0x200f0134, "SVB_PWM", "GPIO0_5", "TEMPER_DQ")
MUXCTRL(CV100_78, 0x200f0138, "GPIO0_6", "SVB_PWM", "TEMPER_DQ")
MUXCTRL(CV100_79, 0x200f013c, "SYS_RSTN_OUT", "GPIO0_7", "TEMPER_DQ")
MUXCTRL(CV100_80, 0x200f0140, "VIU_CLK", "GPIO11_6")
MUXCTRL(CV100_81, 0x200f0144, "VIU_VS", "GPIO11_5")
MUXCTRL(CV100_82, 0x200f0148, "VIU_HS", "GPIO11_4")
MUXCTRL(CV100_83, 0x200f014c, "VIU_DAT11", "GPIO11_3")
MUXCTRL(CV100_84, 0x200f0150, "VIU_DAT10", "GPIO11_2")
MUXCTRL(CV100_85, 0x200f0154, "VIU_DAT9", "GPIO11_1")
MUXCTRL(CV100_86, 0x200f0158, "VIU_DAT8", "GPIO11_0")
MUXCTRL(CV100_87, 0x200f015c, "VIU_DAT7", "GPIO10_7")
MUXCTRL(CV100_88, 0x200f0160, "VIU_DAT6", "GPIO10_6")
MUXCTRL(CV100_89, 0x200f0164, "VIU_DAT5", "GPIO10_5")
MUXCTRL(CV100_90, 0x200f0168, "VIU_DAT4", "GPIO10_4")
MUXCTRL(CV100_91, 0x200f016c, "VIU_DAT3", "GPIO10_3")
MUXCTRL(CV100_92, 0x200f0170, "VIU_DAT2", "GPIO10_2")
MUXCTRL(CV100_93, 0x200f0174, "VIU_DAT1", "GPIO10_1")
MUXCTRL(CV100_94, 0x200f0178, "VIU_DAT0", "GPIO10_0")

static const muxctrl_reg_t *CV100regs[] = {
    &CV100_0,  &CV100_1,  &CV100_2,  &CV100_3,  &CV100_4,  &CV100_5,  &CV100_6,
    &CV100_7,  &CV100_8,  &CV100_9,  &CV100_10, &CV100_11, &CV100_12, &CV100_13,
    &CV100_14, &CV100_15, &CV100_16, &CV100_17, &CV100_18, &CV100_19, &CV100_20,
    &CV100_21, &CV100_22, &CV100_23, &CV100_24, &CV100_25, &CV100_26, &CV100_27,
    &CV100_28, &CV100_29, &CV100_30, &CV100_31, &CV100_32, &CV100_33, &CV100_34,
    &CV100_35, &CV100_36, &CV100_37, &CV100_38, &CV100_39, &CV100_40, &CV100_41,
    &CV100_42, &CV100_43, &CV100_44, &CV100_45, &CV100_46, &CV100_47, &CV100_48,
    &CV100_49, &CV100_50, &CV100_51, &CV100_52, &CV100_53, &CV100_54, &CV100_55,
    &CV100_56, &CV100_57, &CV100_66, &CV100_67, &CV100_68, &CV100_69, &CV100_70,
    &CV100_71, &CV100_72, &CV100_73, &CV100_74, &CV100_75, &CV100_76, &CV100_77,
    &CV100_78, &CV100_79, &CV100_80, &CV100_81, &CV100_82, &CV100_83, &CV100_84,
    &CV100_85, &CV100_86, &CV100_87, &CV100_88, &CV100_89, &CV100_90, &CV100_91,
    &CV100_92, &CV100_93, &CV100_94, 0,
};

MUXCTRL(AV100_0, 0x200f0000, "GPIO0_5", "SENSOR_CLK")
MUXCTRL(AV100_1, 0x200f0004, "GPIO0_6", "FLASH_TRIG", "SPI1_CSN1")
MUXCTRL(AV100_2, 0x200f0008, "GPIO0_7", "SHUTTER_TRIG", "SPI1_CSN2")
MUXCTRL(AV100_3, 0x200f000c, "GPIO1_0", "VO_CLK")
MUXCTRL(AV100_4, 0x200f0010, "GPIO6_0", "VO_DAT15")
MUXCTRL(AV100_5, 0x200f0014, "GPIO6_1", "VO_DAT14")
MUXCTRL(AV100_6, 0x200f0018, "GPIO6_2", "VO_DAT13")
MUXCTRL(AV100_7, 0x200f001c, "GPIO6_3", "VO_DAT12")
MUXCTRL(AV100_8, 0x200f0020, "GPIO6_4", "VO_DAT11", "SFC_NAND_BOOT_PIN2")
MUXCTRL(AV100_9, 0x200f0024, "GPIO6_5", "VO_DAT10", "SFC_NAND_BOOT_PIN1")
MUXCTRL(AV100_10, 0x200f0028, "GPIO6_6", "VO_DAT9", "SFC_NAND_BOOT_PIN0")
MUXCTRL(AV100_11, 0x200f002c, "GPIO6_7", "VO_DAT8")
MUXCTRL(AV100_12, 0x200f0030, "GPIO7_0", "VO_DAT7")
MUXCTRL(AV100_13, 0x200f0034, "GPIO7_1", "VO_DAT6")
MUXCTRL(AV100_14, 0x200f0038, "GPIO7_2", "VO_DAT5")
MUXCTRL(AV100_15, 0x200f003c, "GPIO7_3", "VO_DAT4")
MUXCTRL(AV100_16, 0x200f0040, "GPIO7_4", "VO_DAT3", "SFC_DEVICE_MODE")
MUXCTRL(AV100_17, 0x200f0044, "GPIO7_5", "VO_DAT2")
MUXCTRL(AV100_18, 0x200f0048, "GPIO7_6", "VO_DAT1", "BOOTROM_SEL")
MUXCTRL(AV100_19, 0x200f004c, "GPIO7_7", "VO_DAT0", "BOOT_SEL")
MUXCTRL(AV100_20, 0x200f0050, "GPIO8_0", "SPI0_SCLK", "I2C0_SCL")
MUXCTRL(AV100_21, 0x200f0054, "GPIO8_1", "SPI0_SDO", "I2C0_SDA")
MUXCTRL(AV100_22, 0x200f0058, "GPIO8_2", "SPI0_SDI")
MUXCTRL(AV100_23, 0x200f005c, "GPIO8_3", "SPI0_CSN")
MUXCTRL(AV100_24, 0x200f0060, "GPIO8_4", "SPI1_SCLK", "I2C1_SCL")
MUXCTRL(AV100_25, 0x200f0064, "GPIO8_5", "SPI1_SDO", "I2C1_SDA")
MUXCTRL(AV100_26, 0x200f0068, "GPIO8_6", "SPI1_SDI")
MUXCTRL(AV100_27, 0x200f006c, "GPIO8_7", "SPI1_CSN0")
MUXCTRL(AV100_28, 0x200f0070, "GPIO9_0", "I2C2_SDA")
MUXCTRL(AV100_29, 0x200f0074, "GPIO9_1", "I2C2_SCL")
MUXCTRL(AV100_30, 0x200f0078, "GPIO9_2", "UART1_RTSN", "UART3_RXD")
MUXCTRL(AV100_31, 0x200f007c, "GPIO9_3", "UART1_RXD")
MUXCTRL(AV100_32, 0x200f0080, "GPIO9_4", "UART1_CTSN", "UART3_TXD")
MUXCTRL(AV100_33, 0x200f0084, "GPIO9_5", "UART1_TXD")
MUXCTRL(AV100_34, 0x200f0088, "GPIO9_6", "UART2_RXD", "I2S_BCLK_RX")
MUXCTRL(AV100_35, 0x200f008c, "GPIO9_7", "UART2_TXD", "I2S_WS_RX")
MUXCTRL(AV100_36, 0x200f0090, "GPIO10_0", "JTAG_TRSTN", "I2S_MCLK")
MUXCTRL(AV100_37, 0x200f0094, "GPIO10_1", "JTAG_TCK", "I2S_BCLK_TX")
MUXCTRL(AV100_38, 0x200f0098, "GPIO10_2", "JTAG_TMS", "I2S_WS_TX")
MUXCTRL(AV100_39, 0x200f009c, "GPIO10_3", "JTAG_TDO", "I2S_SD_RX")
MUXCTRL(AV100_40, 0x200f00a0, "GPIO10_4", "JTAG_TDI", "I2S_SD_TX")
MUXCTRL(AV100_41, 0x200f00a4, "GPIO10_5", "IR_IN", "PWM4")
MUXCTRL(AV100_42, 0x200f00a8, "GPIO10_6", "USB_OVRCUR")
MUXCTRL(AV100_43, 0x200f00ac, "GPIO10_7", "USB_PWREN")
MUXCTRL(AV100_44, 0x200f00b0, "GPIO2_0", "SDIO0_CCLK_OUT", "I2S_MCLK")
MUXCTRL(AV100_45, 0x200f00b4, "GPIO2_1", "SDIO0_CARD_POWER_EN", "I2S_BCLK_TX")
MUXCTRL(AV100_46, 0x200f00b8, "GPIO2_2", "SDIO0_CARD_DETECT", "I2S_WS_TX")
MUXCTRL(AV100_47, 0x200f00bc, "GPIO2_3", "SDIO0_CWPR", "I2S_SD_TX")
MUXCTRL(AV100_48, 0x200f00c0, "GPIO2_4", "SDIO0_CCMD", "I2S_BCLK_RX")
MUXCTRL(AV100_49, 0x200f00c4, "GPIO2_5", "SDIO0_CDATA0", "I2S_WS_RX")
MUXCTRL(AV100_50, 0x200f00c8, "GPIO2_6", "SDIO0_CDATA1", "I2S_SD_RX")
MUXCTRL(AV100_51, 0x200f00cc, "GPIO2_7", "SDIO0_CDATA2")
MUXCTRL(AV100_52, 0x200f00d0, "GPIO1_1", "SDIO0_CDATA3")
MUXCTRL(AV100_53, 0x200f00d4, "SENSOR_RSTN", "GPIO0_0", "TEMPER_DQ")
MUXCTRL(AV100_54, 0x200f00d8, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(AV100_55, 0x200f00dc, "GPIO0_2", "PWM5", "TEMPER_DQ")
MUXCTRL(AV100_56, 0x200f00e0, "GPIO0_3", "PWM6", "TEMPER_DQ")
MUXCTRL(AV100_57, 0x200f00e4, "GPIO0_4", "PWM7", "TEMPER_DQ")
MUXCTRL(AV100_58, 0x200f00e8, "GPIO11_0", "SDIO1_CCLK_OUT")
MUXCTRL(AV100_59, 0x200f00ec, "GPIO11_1", "SDIO1_CARD_POWER_EN")
MUXCTRL(AV100_60, 0x200f00f0, "GPIO11_2", "SDIO1_CARD_DETECT")
MUXCTRL(AV100_61, 0x200f00f4, "GPIO11_3", "SDIO1_CWPR")
MUXCTRL(AV100_62, 0x200f00f8, "GPIO11_4", "SDIO1_CCMD")
MUXCTRL(AV100_63, 0x200f00fc, "GPIO11_5", "SDIO1_CDATA0", "CLK_TEST_OUT0",
        "CLK_TEST_OUT1", "CLK_TEST_OUT2", "CLK_TEST_OUT3", "RTC_TEST_CLK",
        "OSC_TEST_CLK")
MUXCTRL(AV100_64, 0x200f0100, "PLL_TEST_OUT0", "SDIO1_CDATA1", "PLL_TEST_OUT1",
        "PLL_TEST_OUT2", "PLL_TEST_OUT3", "GPIO11_6")
MUXCTRL(AV100_65, 0x200f0104, "GPIO11_7", "SDIO1_CDATA2")
MUXCTRL(AV100_66, 0x200f0108, "GPIO1_2", "SDIO1_CDATA3")
MUXCTRL(AV100_67, 0x200f010c, "NF_DQ0", "GPIO5_0")
MUXCTRL(AV100_68, 0x200f0110, "NF_DQ1", "GPIO5_1")
MUXCTRL(AV100_69, 0x200f0114, "NF_DQ2", "GPIO5_2")
MUXCTRL(AV100_70, 0x200f0118, "NF_DQ3", "GPIO5_3")
MUXCTRL(AV100_71, 0x200f011c, "NF_DQ4", "GPIO5_4")
MUXCTRL(AV100_72, 0x200f0120, "NF_DQ5", "GPIO5_5")
MUXCTRL(AV100_73, 0x200f0124, "NF_DQ6", "GPIO5_6")
MUXCTRL(AV100_74, 0x200f0128, "NF_DQ7", "GPIO5_7")
MUXCTRL(AV100_75, 0x200f012c, "NF_RDY0", "GPIO3_0")
MUXCTRL(AV100_76, 0x200f0130, "NF_RDY1", "GPIO3_1")
MUXCTRL(AV100_77, 0x200f0134, "NF_REN", "GPIO3_2")
MUXCTRL(AV100_78, 0x200f0138, "NF_CSN0", "GPIO3_3")
MUXCTRL(AV100_79, 0x200f013c, "NF_CSN1", "GPIO3_4", "SFC_CSN0")
MUXCTRL(AV100_80, 0x200f0140, "NF_CLE", "GPIO3_5")
MUXCTRL(AV100_81, 0x200f0144, "NF_ALE", "GPIO3_6")
MUXCTRL(AV100_82, 0x200f0148, "NF_WEN", "GPIO3_7")
MUXCTRL(AV100_83, 0x200f014c, "PWM0", "GPIO14_0", "PMC_I2C_SCL")
MUXCTRL(AV100_84, 0x200f0150, "PWM1", "GPIO14_1", "PMC_I2C_SDA")
MUXCTRL(AV100_85, 0x200f0154, "PWM2", "GPIO14_2")
MUXCTRL(AV100_86, 0x200f0158, "PWM3", "GPIO14_3")
MUXCTRL(AV100_87, 0x200f015c, "SAR_ADC_CH0", "GPIO1_6")
MUXCTRL(AV100_88, 0x200f0160, "SAR_ADC_CH1", "GPIO1_7")
MUXCTRL(AV100_89, 0x200f0164, "GPIO14_4", "EPHY_CLK")
MUXCTRL(AV100_90, 0x200f0168, "GPIO14_5", "MDCK")
MUXCTRL(AV100_91, 0x200f016c, "GPIO14_6", "MDIO")
MUXCTRL(AV100_92, 0x200f0170, "GPIO14_7", "RGMII_TX_EN")
MUXCTRL(AV100_93, 0x200f0174, "GPIO4_0", "RGMII_TX_CLK",
        "RMII_CLK_OUT/MII_TX_CLK")
MUXCTRL(AV100_94, 0x200f0178, "GPIO4_1", "RGMII_TXD0")
MUXCTRL(AV100_95, 0x200f017c, "GPIO4_2", "RGMII_TXD1")
MUXCTRL(AV100_96, 0x200f0180, "GPIO4_3", "RGMII_TXD2")
MUXCTRL(AV100_97, 0x200f0184, "GPIO4_4", "RGMII_TXD3")
MUXCTRL(AV100_98, 0x200f0188, "GPIO4_5", "RGMII_RX_CLK")
MUXCTRL(AV100_99, 0x200f018c, "GPIO4_6", "RGMII_RX_DV")
MUXCTRL(AV100_100, 0x200f0190, "GPIO4_7", "RGMII_RXD0")
MUXCTRL(AV100_101, 0x200f0194, "GPIO1_3", "RGMII_RXD1")
MUXCTRL(AV100_102, 0x200f0198, "GPIO1_4", "RGMII_RXD2")
MUXCTRL(AV100_103, 0x200f019c, "GPIO1_5", "RGMII_RXD3")
MUXCTRL(AV100_104, 0x200f01a0, "GPIO15_0", "VI_CLK")
MUXCTRL(AV100_105, 0x200f01a4, "GPIO15_1", "VI_HS")
MUXCTRL(AV100_106, 0x200f01a8, "GPIO15_2", "VI_VS")
MUXCTRL(AV100_107, 0x200f01ac, "GPIO12_0", "VI_DAT15", "I2S_MCLK")
MUXCTRL(AV100_108, 0x200f01b0, "GPIO12_1", "VI_DAT14", "I2S_BCLK_TX")
MUXCTRL(AV100_109, 0x200f01b4, "GPIO12_2", "VI_DAT13", "I2S_WS_TX")
MUXCTRL(AV100_110, 0x200f01b8, "GPIO12_3", "VI_DAT12", "I2S_SD_TX")
MUXCTRL(AV100_111, 0x200f01bc, "GPIO12_4", "VI_DAT11", "I2S_BCLK_RX")
MUXCTRL(AV100_112, 0x200f01c0, "GPIO12_5", "VI_DAT10", "I2S_WS_RX")
MUXCTRL(AV100_113, 0x200f01c4, "GPIO12_6", "VI_DAT9", "I2S_SD_RX")
MUXCTRL(AV100_114, 0x200f01c8, "GPIO12_7", "VI_DAT8")
MUXCTRL(AV100_115, 0x200f01cc, "GPIO13_0", "VI_DAT7")
MUXCTRL(AV100_116, 0x200f01d0, "GPIO13_1", "VI_DAT6")
MUXCTRL(AV100_117, 0x200f01d4, "GPIO13_2", "VI_DAT5")
MUXCTRL(AV100_118, 0x200f01d8, "GPIO13_3", "VI_DAT4")
MUXCTRL(AV100_119, 0x200f01dc, "GPIO13_4", "VI_DAT3")
MUXCTRL(AV100_120, 0x200f01e0, "GPIO13_5", "VI_DAT2")
MUXCTRL(AV100_121, 0x200f01e4, "GPIO13_6", "VI_DAT1")
MUXCTRL(AV100_122, 0x200f01e8, "GPIO13_7", "VI_DAT0", "PWM4")

static const muxctrl_reg_t *AV100regs[] = {
    &AV100_0,   &AV100_1,   &AV100_2,   &AV100_3,   &AV100_4,   &AV100_5,
    &AV100_6,   &AV100_7,   &AV100_8,   &AV100_9,   &AV100_10,  &AV100_11,
    &AV100_12,  &AV100_13,  &AV100_14,  &AV100_15,  &AV100_16,  &AV100_17,
    &AV100_18,  &AV100_19,  &AV100_20,  &AV100_21,  &AV100_22,  &AV100_23,
    &AV100_24,  &AV100_25,  &AV100_26,  &AV100_27,  &AV100_28,  &AV100_29,
    &AV100_30,  &AV100_31,  &AV100_32,  &AV100_33,  &AV100_34,  &AV100_35,
    &AV100_36,  &AV100_37,  &AV100_38,  &AV100_39,  &AV100_40,  &AV100_41,
    &AV100_42,  &AV100_43,  &AV100_44,  &AV100_45,  &AV100_46,  &AV100_47,
    &AV100_48,  &AV100_49,  &AV100_50,  &AV100_51,  &AV100_52,  &AV100_53,
    &AV100_54,  &AV100_55,  &AV100_56,  &AV100_57,  &AV100_58,  &AV100_59,
    &AV100_60,  &AV100_61,  &AV100_62,  &AV100_63,  &AV100_64,  &AV100_65,
    &AV100_66,  &AV100_67,  &AV100_68,  &AV100_69,  &AV100_70,  &AV100_71,
    &AV100_72,  &AV100_73,  &AV100_74,  &AV100_75,  &AV100_76,  &AV100_77,
    &AV100_78,  &AV100_79,  &AV100_80,  &AV100_81,  &AV100_82,  &AV100_83,
    &AV100_84,  &AV100_85,  &AV100_86,  &AV100_87,  &AV100_88,  &AV100_89,
    &AV100_90,  &AV100_91,  &AV100_92,  &AV100_93,  &AV100_94,  &AV100_95,
    &AV100_96,  &AV100_97,  &AV100_98,  &AV100_99,  &AV100_100, &AV100_101,
    &AV100_102, &AV100_103, &AV100_104, &AV100_105, &AV100_106, &AV100_107,
    &AV100_108, &AV100_109, &AV100_110, &AV100_111, &AV100_112, &AV100_113,
    &AV100_114, &AV100_115, &AV100_116, &AV100_117, &AV100_118, &AV100_119,
    &AV100_120, &AV100_121, &AV100_122, 0,
};

MUXCTRL(CV200_0, 0x200f0000, "GPIO0_4", "SENSOR_CLK")
MUXCTRL(CV200_1, 0x200f0004, "SENSOR_RSTN", "GPIO0_5")
MUXCTRL(CV200_2, 0x200f0008, "GPIO0_6", "FLASH_TRIG", "SFC_EMMC_BOOT_MODE",
        "SPI1_CSN1", "VI_VS_BT1120")
MUXCTRL(CV200_3, 0x200f000c, "GPIO0_7", "SHUTTER_TRIG", "SFC_DEVICE_MODE",
        "VI_HS_BT1120")
MUXCTRL(CV200_4, 0x200f0010, "GPIO2_0", "RMII_CLK", "VO_CLK", "SDIO1_CCLK_OUT")
MUXCTRL(CV200_5, 0x200f0014, "GPIO2_1", "RMII_TX_EN", "VO_VS",
        "SDIO1_CARD_DETECT")
MUXCTRL(CV200_6, 0x200f0018, "GPIO2_2", "RMII_TXD0", "VO_DATA5", "SDIO1_CWPR")
MUXCTRL(CV200_7, 0x200f001c, "GPIO2_3", "RMII_TXD1", "VO_DE", "SDIO1_CDATA1")
MUXCTRL(CV200_8, 0x200f0020, "GPIO2_4", "RMII_RX_DV", "VO_DATA7",
        "SDIO1_CDATA0")
MUXCTRL(CV200_9, 0x200f0024, "GPIO2_5", "RMII_RXD0", "VO_DATA2", "SDIO1_CDATA3")
MUXCTRL(CV200_10, 0x200f0028, "GPIO2_6", "RMII_RXD1", "VO_DATA3", "SDIO1_CCMD")
MUXCTRL(CV200_11, 0x200f002c, "GPIO2_7", "EPHY_RST", "BOOT_SEL", "VO_HS",
        "SDIO1_CARD_POWER_EN")
MUXCTRL(CV200_12, 0x200f0030, "GPIO0_3", "SPI1_CSN1", "VO_DATA0")
MUXCTRL(CV200_13, 0x200f0034, "GPIO3_0", "EPHY_CLK", "VO_DATA1", "SDIO1_CDATA2")
MUXCTRL(CV200_14, 0x200f0038, "GPIO3_1", "MDCK", "BOOTROM_SEL", "VO_DATA6")
MUXCTRL(CV200_15, 0x200f003c, "GPIO3_2", "MDIO", "VO_DATA4")
MUXCTRL(CV200_16, 0x200f0040, "GPIO3_3", "SPI0_SCLK", "I2C0_SCL")
MUXCTRL(CV200_17, 0x200f0044, "GPIO3_4", "SPI0_SDO", "I2C0_SDA")
MUXCTRL(CV200_18, 0x200f0048, "GPIO3_5", "SPI0_SDI")
MUXCTRL(CV200_19, 0x200f004c, "GPIO3_6", "SPI0_CSN")
MUXCTRL(CV200_20, 0x200f0050, "GPIO3_7", "SPI1_SCLK", "I2C1_SCL")
MUXCTRL(CV200_21, 0x200f0054, "GPIO4_0", "SPI1_SDO", "I2C1_SDA")
MUXCTRL(CV200_22, 0x200f0058, "GPIO4_1", "SPI1_SDI")
MUXCTRL(CV200_23, 0x200f005c, "GPIO4_2", "SPI1_CSN0")
MUXCTRL(CV200_24, 0x200f0060, "GPIO4_3", "I2C2_SDA")
MUXCTRL(CV200_25, 0x200f0064, "GPIO4_4", "I2C2_SCL")
MUXCTRL(CV200_26, 0x200f0068, "GPIO4_5", "USB_OVRCUR")
MUXCTRL(CV200_27, 0x200f006c, "GPIO4_6", "USB_PWREN")
MUXCTRL(CV200_28, 0x200f0070, "GPIO0_0", "IR_IN", "TEMPER_DQ")
MUXCTRL(CV200_29, 0x200f0074, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(CV200_30, 0x200f0078, "GPIO0_2", "TEMPER_DQ")
MUXCTRL(CV200_31, 0x200f007c, "GPIO1_0", "VI_DATA13", "I2S_BCLK_TX", "PWM0")
MUXCTRL(CV200_32, 0x200f0080, "GPIO1_1", "VI_DATA10", "I2S_SD_TX", "UART1_TXD")
MUXCTRL(CV200_33, 0x200f0084, "GPIO1_2", "VI_DATA12", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(CV200_34, 0x200f0088, "GPIO1_3", "VI_DATA11", "I2S_WS_TX", "UART2_RXD")
MUXCTRL(CV200_35, 0x200f008c, "GPIO1_4", "VI_DATA15", "VI_VS_SEN", "I2S_WS_RX",
        "UART1_RXD")
MUXCTRL(CV200_36, 0x200f0090, "GPIO1_5", "VI_DATA14", "VI_HS_SEN",
        "I2S_BCLK_RX", "UART1_RTSN")
MUXCTRL(CV200_37, 0x200f0094, "GPIO1_6", "VI_DATA9", "I2S_SD_RX", "UART2_TXD")
MUXCTRL(CV200_38, 0x200f0098, "GPIO1_7", "SDIO0_CARD_POWER_EN")
MUXCTRL(CV200_39, 0x200f009c, "GPIO4_7", "SDIO0_CARD_DETECT")
MUXCTRL(CV200_40, 0x200f00a0, "GPIO5_0", "SDIO0_CWPR")
MUXCTRL(CV200_41, 0x200f00a4, "GPIO5_1", "SDIO0_CCLK_OUT")
MUXCTRL(CV200_42, 0x200f00a8, "GPIO5_2", "SDIO0_CCMD")
MUXCTRL(CV200_43, 0x200f00ac, "GPIO5_3", "SDIO0_CDATA0")
MUXCTRL(CV200_44, 0x200f00b0, "TEST_CLK", "SDIO0_CDATA1", "GPIO5_4")
MUXCTRL(CV200_45, 0x200f00b4, "GPIO5_5", "SDIO0_CDATA2")
MUXCTRL(CV200_46, 0x200f00b8, "GPIO5_6", "SDIO0_CDATA3")
MUXCTRL(CV200_47, 0x200f00bc, "GPIO5_7", "EMMC_DATA6", "I2S_SD_TX",
        "UART1_RTSN")
MUXCTRL(CV200_48, 0x200f00c0, "GPIO6_0", "EMMC_DATA5", "I2S_WS_TX", "UART1_RXD")
MUXCTRL(CV200_49, 0x200f00c4, "GPIO6_1", "EMMC_DATA7", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(CV200_50, 0x200f00c8, "GPIO6_2", "EMMC_DS", "I2S_SD_RX", "UART1_TXD")
MUXCTRL(CV200_51, 0x200f00cc, "GPIO6_3", "EMMC_DATA1", "UART2_RXD")
MUXCTRL(CV200_52, 0x200f00d0, "GPIO6_4", "EMMC_DATA2", "I2S_BCLK_TX",
        "UART2_TXD")
MUXCTRL(CV200_53, 0x200f00d4, "GPIO6_5", "JTAG_TRSTN", "SPI1_CSN1", "I2S_MCLK")
MUXCTRL(CV200_54, 0x200f00d8, "GPIO6_6", "JTAG_TCK", "SPI1_SCLK", "I2S_WS_TX",
        "I2C1_SCL")
MUXCTRL(CV200_55, 0x200f00dc, "GPIO6_7", "JTAG_TMS", "SPI1_CSN0", "I2S_SD_TX")
MUXCTRL(CV200_56, 0x200f00e0, "GPIO7_0", "JTAG_TDO", "SPI1_SDO", "I2S_SD_RX",
        "I2C1_SDA")
MUXCTRL(CV200_57, 0x200f00e4, "GPIO7_1", "JTAG_TDI", "SPI1_SDI", "I2S_BCLK_TX")
MUXCTRL(CV200_58, 0x200f00e8, "PMC_PWM", "GPIO7_2", "PWM0")
MUXCTRL(CV200_59, 0x200f00ec, "PWM1", "GPIO7_3")
MUXCTRL(CV200_60, 0x200f00f0, "PWM2", "GPIO7_4", "SPI1_CSN1")
MUXCTRL(CV200_61, 0x200f00f4, "PWM3", "GPIO7_5")
MUXCTRL(CV200_62, 0x200f00f8, "SAR_ADC_CH0", "GPIO7_6")
MUXCTRL(CV200_63, 0x200f00fc, "SAR_ADC_CH1", "GPIO7_7")
MUXCTRL(CV200_64, 0x200f0100, "SAR_ADC_CH2", "GPIO8_0")
MUXCTRL(CV200_65, 0x200f0104, "SAR_ADC_CH3", "GPIO8_1")

static const muxctrl_reg_t *CV200regs[] = {
    &CV200_0,  &CV200_1,  &CV200_2,  &CV200_3,  &CV200_4,  &CV200_5,  &CV200_6,
    &CV200_7,  &CV200_8,  &CV200_9,  &CV200_10, &CV200_11, &CV200_12, &CV200_13,
    &CV200_14, &CV200_15, &CV200_16, &CV200_17, &CV200_18, &CV200_19, &CV200_20,
    &CV200_21, &CV200_22, &CV200_23, &CV200_24, &CV200_25, &CV200_26, &CV200_27,
    &CV200_28, &CV200_29, &CV200_30, &CV200_31, &CV200_32, &CV200_33, &CV200_34,
    &CV200_35, &CV200_36, &CV200_37, &CV200_38, &CV200_39, &CV200_40, &CV200_41,
    &CV200_42, &CV200_43, &CV200_44, &CV200_45, &CV200_46, &CV200_47, &CV200_48,
    &CV200_49, &CV200_50, &CV200_51, &CV200_52, &CV200_53, &CV200_54, &CV200_55,
    &CV200_56, &CV200_57, &CV200_58, &CV200_59, &CV200_60, &CV200_61, &CV200_62,
    &CV200_63, &CV200_64, &CV200_65, 0,
};

MUXCTRL(EV20X_0, 0x200f0000, "GPIO0_4", "SENSOR_CLK")
MUXCTRL(EV20X_1, 0x200f0004, "SENSOR_RSTN", "GPIO0_5")
MUXCTRL(EV20X_2, 0x200f0008, "GPIO0_6", "FLASH_TRIG", "SFC_EMMC_BOOT_MODE",
        "SPI1_CSN1", "VI_VS_BT1120")
MUXCTRL(EV20X_3, 0x200f000c, "GPIO0_7", "SHUTTER_TRIG", "SFC_DEVICE_MODE",
        "VI_HS_BT1120")
MUXCTRL(EV20X_4, 0x200f0010, "GPIO2_0", "RMII_CLK", "VO_CLK", "SDIO1_CCLK_OUT")
MUXCTRL(EV20X_5, 0x200f0014, "GPIO2_1", "RMII_TX_EN", "VO_VS",
        "SDIO1_CARD_DETECT")
MUXCTRL(EV20X_6, 0x200f0018, "GPIO2_2", "RMII_TXD0", "VO_DATA5", "SDIO1_CWPR")
MUXCTRL(EV20X_7, 0x200f001c, "GPIO2_3", "RMII_TXD1", "VO_DE", "SDIO1_CDATA1")
MUXCTRL(EV20X_8, 0x200f0020, "GPIO2_4", "RMII_RX_DV", "VO_DATA7",
        "SDIO1_CDATA0")
MUXCTRL(EV20X_9, 0x200f0024, "GPIO2_5", "RMII_RXD0", "VO_DATA2", "SDIO1_CDATA3")
MUXCTRL(EV20X_10, 0x200f0028, "GPIO2_6", "RMII_RXD1", "VO_DATA3", "SDIO1_CCMD")
MUXCTRL(EV20X_11, 0x200f002c, "GPIO2_7", "EPHY_RST", "BOOT_SEL", "VO_HS",
        "SDIO1_CARD_POWER_EN")
MUXCTRL(EV20X_12, 0x200f0030, "GPIO0_3", "SPI1_CSN1", "VO_DATA0")
MUXCTRL(EV20X_13, 0x200f0034, "GPIO3_0", "EPHY_CLK", "VO_DATA1", "SDIO1_CDATA2")
MUXCTRL(EV20X_14, 0x200f0038, "GPIO3_1", "MDCK", "BOOTROM_SEL", "VO_DATA6")
MUXCTRL(EV20X_15, 0x200f003c, "GPIO3_2", "MDIO", "VO_DATA4")
MUXCTRL(EV20X_16, 0x200f0040, "GPIO3_3", "SPI0_SCLK", "I2C0_SCL")
MUXCTRL(EV20X_17, 0x200f0044, "GPIO3_4", "SPI0_SDO", "I2C0_SDA")
MUXCTRL(EV20X_18, 0x200f0048, "GPIO3_5", "SPI0_SDI")
MUXCTRL(EV20X_19, 0x200f004c, "GPIO3_6", "SPI0_CSN")
MUXCTRL(EV20X_20, 0x200f0050, "GPIO3_7", "SPI1_SCLK", "I2C1_SCL")
MUXCTRL(EV20X_21, 0x200f0054, "GPIO4_0", "SPI1_SDO", "I2C1_SDA")
MUXCTRL(EV20X_22, 0x200f0058, "GPIO4_1", "SPI1_SDI")
MUXCTRL(EV20X_23, 0x200f005c, "GPIO4_2", "SPI1_CSN0")
MUXCTRL(EV20X_24, 0x200f0060, "GPIO4_3", "I2C2_SDA")
MUXCTRL(EV20X_25, 0x200f0064, "GPIO4_4", "I2C2_SCL")
MUXCTRL(EV20X_26, 0x200f0068, "GPIO4_5", "USB_OVRCUR")
MUXCTRL(EV20X_27, 0x200f006c, "GPIO4_6", "USB_PWREN")
MUXCTRL(EV20X_28, 0x200f0070, "GPIO0_0", "IR_IN", "TEMPER_DQ")
MUXCTRL(EV20X_29, 0x200f0074, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(EV20X_30, 0x200f0078, "GPIO0_2", "TEMPER_DQ")
MUXCTRL(EV20X_31, 0x200f007c, "GPIO1_0", "VI_DATA13", "I2S_BCLK_TX", "PWM0")
MUXCTRL(EV20X_32, 0x200f0080, "GPIO1_1", "VI_DATA10", "I2S_SD_TX", "UART1_TXD")
MUXCTRL(EV20X_33, 0x200f0084, "GPIO1_2", "VI_DATA12", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(EV20X_34, 0x200f0088, "GPIO1_3", "VI_DATA11", "I2S_WS_TX", "UART2_RXD")
MUXCTRL(EV20X_35, 0x200f008c, "GPIO1_4", "VI_DATA15", "VI_VS_SEN", "I2S_WS_RX",
        "UART1_RXD")
MUXCTRL(EV20X_36, 0x200f0090, "GPIO1_5", "VI_DATA14", "VI_HS_SEN",
        "I2S_BCLK_RX", "UART1_RTSN")
MUXCTRL(EV20X_37, 0x200f0094, "GPIO1_6", "VI_DATA9", "I2S_SD_RX", "UART2_TXD")
MUXCTRL(EV20X_38, 0x200f0098, "GPIO1_7", "SDIO0_CARD_POWER_EN")
MUXCTRL(EV20X_39, 0x200f009c, "GPIO4_7", "SDIO0_CARD_DETECT")
MUXCTRL(EV20X_40, 0x200f00a0, "GPIO5_0", "SDIO0_CWPR")
MUXCTRL(EV20X_41, 0x200f00a4, "GPIO5_1", "SDIO0_CCLK_OUT")
MUXCTRL(EV20X_42, 0x200f00a8, "GPIO5_2", "SDIO0_CCMD")
MUXCTRL(EV20X_43, 0x200f00ac, "GPIO5_3", "SDIO0_CDATA0")
MUXCTRL(EV20X_44, 0x200f00b0, "TEST_CLK", "SDIO0_CDATA1", "GPIO5_4")
MUXCTRL(EV20X_45, 0x200f00b4, "GPIO5_5", "SDIO0_CDATA2")
MUXCTRL(EV20X_46, 0x200f00b8, "GPIO5_6", "SDIO0_CDATA3")
MUXCTRL(EV20X_47, 0x200f00bc, "GPIO5_7", "EMMC_DATA6", "I2S_SD_TX",
        "UART1_RTSN")
MUXCTRL(EV20X_48, 0x200f00c0, "GPIO6_0", "EMMC_DATA5", "I2S_WS_TX", "UART1_RXD")
MUXCTRL(EV20X_49, 0x200f00c4, "GPIO6_1", "EMMC_DATA7", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(EV20X_50, 0x200f00c8, "GPIO6_2", "EMMC_DS", "I2S_SD_RX", "UART1_TXD")
MUXCTRL(EV20X_51, 0x200f00cc, "GPIO6_3", "EMMC_DATA1", "UART2_RXD")
MUXCTRL(EV20X_52, 0x200f00d0, "GPIO6_4", "EMMC_DATA2", "I2S_BCLK_TX",
        "UART2_TXD")
MUXCTRL(EV20X_53, 0x200f00d4, "GPIO6_5", "JTAG_TRSTN", "SPI1_CSN1", "I2S_MCLK")
MUXCTRL(EV20X_54, 0x200f00d8, "GPIO6_6", "JTAG_TCK", "SPI1_SCLK", "I2S_WS_TX",
        "I2C1_SCL")
MUXCTRL(EV20X_55, 0x200f00dc, "GPIO6_7", "JTAG_TMS", "SPI1_CSN0", "I2S_SD_TX")
MUXCTRL(EV20X_56, 0x200f00e0, "GPIO7_0", "JTAG_TDO", "SPI1_SDO", "I2S_SD_RX",
        "I2C1_SDA")
MUXCTRL(EV20X_57, 0x200f00e4, "GPIO7_1", "JTAG_TDI", "SPI1_SDI", "I2S_BCLK_TX")
MUXCTRL(EV20X_58, 0x200f00e8, "PMC_PWM", "GPIO7_2", "PWM0")
MUXCTRL(EV20X_59, 0x200f00ec, "PWM1", "GPIO7_3")
MUXCTRL(EV20X_60, 0x200f00f0, "PWM2", "GPIO7_4", "SPI1_CSN1")
MUXCTRL(EV20X_61, 0x200f00f4, "PWM3", "GPIO7_5")
MUXCTRL(EV20X_62, 0x200f00f8, "SAR_ADC_CH0", "GPIO7_6")
MUXCTRL(EV20X_63, 0x200f00fc, "SAR_ADC_CH1", "GPIO7_7")
MUXCTRL(EV20X_64, 0x200f0100, "SAR_ADC_CH2", "GPIO8_0")
MUXCTRL(EV20X_65, 0x200f0104, "SAR_ADC_CH3", "GPIO8_1")

static const muxctrl_reg_t *EV20Xregs[] = {
    &EV20X_0,  &EV20X_1,  &EV20X_2,  &EV20X_3,  &EV20X_4,  &EV20X_5,  &EV20X_6,
    &EV20X_7,  &EV20X_8,  &EV20X_9,  &EV20X_10, &EV20X_11, &EV20X_12, &EV20X_13,
    &EV20X_14, &EV20X_15, &EV20X_16, &EV20X_17, &EV20X_18, &EV20X_19, &EV20X_20,
    &EV20X_21, &EV20X_22, &EV20X_23, &EV20X_24, &EV20X_25, &EV20X_26, &EV20X_27,
    &EV20X_28, &EV20X_29, &EV20X_30, &EV20X_31, &EV20X_32, &EV20X_33, &EV20X_34,
    &EV20X_35, &EV20X_36, &EV20X_37, &EV20X_38, &EV20X_39, &EV20X_40, &EV20X_41,
    &EV20X_42, &EV20X_43, &EV20X_44, &EV20X_45, &EV20X_46, &EV20X_47, &EV20X_48,
    &EV20X_49, &EV20X_50, &EV20X_51, &EV20X_52, &EV20X_53, &EV20X_54, &EV20X_55,
    &EV20X_56, &EV20X_57, &EV20X_58, &EV20X_59, &EV20X_60, &EV20X_61, &EV20X_62,
    &EV20X_63, &EV20X_64, &EV20X_65, 0,
};

MUXCTRL(AV200_muxctrl_reg0, 0x12040000, "GPIO1_0", "FLASH_TRIG", "SPI2_CSN1",
        "PWM4")
MUXCTRL(AV200_muxctrl_reg1, 0x12040004, "GPIO1_1", "SHUTTER_TRIG", "reserved",
        "PWM5")
MUXCTRL(AV200_muxctrl_reg2, 0x12040008, "GPIO0_0", "SENSOR1_CLK")
MUXCTRL(AV200_muxctrl_reg3, 0x1204000C, "SENSOR1_RSTN", "GPIO0_1")
MUXCTRL(AV200_muxctrl_reg4, 0x12040010, "GPIO0_2", "SENSOR0_HS", "SENSOR1_HS")
MUXCTRL(AV200_muxctrl_reg5, 0x12040014, "GPIO0_3", "SENSOR0_VS", "SENSOR1_VS")
MUXCTRL(AV200_muxctrl_reg6, 0x12040018, "GPIO0_4", "SPI1_SCLK", "I2C1_SCL",
        "SPI1_3WIRE_CLK")
MUXCTRL(AV200_muxctrl_reg7, 0x1204001C, "GPIO0_5", "SPI1_SDO", "I2C1_SDA",
        "SPI1_3WIRE_DATA")
MUXCTRL(AV200_muxctrl_reg8, 0x12040020, "GPIO0_6", "SPI1_SDI")
MUXCTRL(AV200_muxctrl_reg9, 0x12040024, "GPIO0_7", "SPI1_CSN", "reserved",
        "SPI1_3WIRE_CSN")
MUXCTRL(AV200_muxctrl_reg10, 0x12040028, "GPIO3_0", "VI1_HS")
MUXCTRL(AV200_muxctrl_reg11, 0x1204002C, "GPIO2_0", "VI1_VS")
MUXCTRL(AV200_muxctrl_reg12, 0x12040030, "GPIO2_1", "VI1_CLK")
MUXCTRL(AV200_muxctrl_reg13, 0x12040034, "GPIO2_2", "VI1_DATA0")
MUXCTRL(AV200_muxctrl_reg14, 0x12040038, "GPIO2_3", "VI1_DATA1")
MUXCTRL(AV200_muxctrl_reg15, 0x1204003C, "GPIO2_4", "VI1_DATA2")
MUXCTRL(AV200_muxctrl_reg16, 0x12040040, "GPIO2_5", "VI1_DATA3")
MUXCTRL(AV200_muxctrl_reg17, 0x12040044, "GPIO2_6", "VI1_DATA4")
MUXCTRL(AV200_muxctrl_reg18, 0x12040048, "GPIO2_7", "VI1_DATA5")
MUXCTRL(AV200_muxctrl_reg19, 0x1204004C, "GPIO1_2", "SPI2_SCLK", "I2S_BCLK_RX")
MUXCTRL(AV200_muxctrl_reg20, 0x12040050, "GPIO1_3", "SPI2_SDO", "I2S_WS_RX")
MUXCTRL(AV200_muxctrl_reg21, 0x12040054, "GPIO1_4", "SPI2_SDI")
MUXCTRL(AV200_muxctrl_reg22, 0x12040058, "GPIO1_5", "SPI2_CSN0")
MUXCTRL(AV200_muxctrl_reg23, 0x1204005C, "GPIO1_6", "I2C2_SDA")
MUXCTRL(AV200_muxctrl_reg24, 0x12040060, "GPIO1_7", "I2C2_SCL")
MUXCTRL(AV200_muxctrl_reg25, 0x12040064, "GPIO3_1", "JTAG_TRSTN", "I2S_WS_TX",
        "PWM4")
MUXCTRL(AV200_muxctrl_reg26, 0x12040068, "GPIO3_2", "JTAG_TCK", "I2S_MCLK",
        "PWM5")
MUXCTRL(AV200_muxctrl_reg27, 0x1204006C, "GPIO3_3", "JTAG_TMS", "I2S_BCLK_TX",
        "PWM6")
MUXCTRL(AV200_muxctrl_reg28, 0x12040070, "GPIO3_4", "JTAG_TDO", "I2S_SD_TX",
        "PWM7")
MUXCTRL(AV200_muxctrl_reg29, 0x12040074, "GPIO3_5", "JTAG_TDI", "I2S_SD_RX",
        "IR_IN")
MUXCTRL(AV200_muxctrl_reg30, 0x12040078, "PMC_PWM0", "GPIO3_6", "reserved",
        "PWM0")
MUXCTRL(AV200_muxctrl_reg31, 0x1204007C, "PMC_PWM1", "GPIO3_7", "reserved",
        "PWM1")
MUXCTRL(AV200_muxctrl_reg32, 0x12040080, "PMC_PWM2", "GPIO4_0", "reserved",
        "PWM2")
MUXCTRL(AV200_muxctrl_reg33, 0x12040084, "PMC_PWM3", "GPIO4_1", "reserved",
        "PWM3")
MUXCTRL(AV200_muxctrl_reg34, 0x12040088, "GPIO5_0", "UART1_RTSN", "UART3_RXD",
        "PWM3")
MUXCTRL(AV200_muxctrl_reg35, 0x1204008C, "GPIO5_1", "UART1_RXD")
MUXCTRL(AV200_muxctrl_reg36, 0x12040090, "GPIO5_2", "UART1_CTSN", "UART3_TXD")
MUXCTRL(AV200_muxctrl_reg37, 0x12040094, "GPIO5_3", "UART1_TXD")
MUXCTRL(AV200_muxctrl_reg38, 0x12040098, "GPIO5_4", "UART2_RXD", "reserved",
        "PWM4")
MUXCTRL(AV200_muxctrl_reg39, 0x1204009C, "GPIO5_5", "UART2_TXD", "reserved",
        "PWM5")
MUXCTRL(AV200_muxctrl_reg40, 0x120400A0, "GPIO5_6", "UART2_RTSN", "UART4_RXD",
        "PWM6", "reserved", "TEMPER_DQ")
MUXCTRL(AV200_muxctrl_reg41, 0x120400A4, "GPIO5_7", "UART2_CTSN", "UART4_TXD",
        "PWM7")
MUXCTRL(AV200_muxctrl_reg42, 0x120400A8, "GPIO4_2", "USB3_PWREN",
        "PCIE_CLK_REQ_N")
MUXCTRL(AV200_muxctrl_reg43, 0x120400AC, "GPIO4_3", "SDIO0_CARD_POWER_EN")
MUXCTRL(AV200_muxctrl_reg44, 0x120400B0, "GPIO6_0", "SDIO0_CARD_DETECT")
MUXCTRL(AV200_muxctrl_reg45, 0x120400B4, "GPIO6_1", "SDIO0_CWPR")
MUXCTRL(AV200_muxctrl_reg46, 0x120400B8, "GPIO6_2", "SDIO0_CCLK_OUT")
MUXCTRL(AV200_muxctrl_reg47, 0x120400BC, "GPIO6_3", "SDIO0_CCMD")
MUXCTRL(AV200_muxctrl_reg48, 0x120400C0, "GPIO6_4", "SDIO0_CDATA0")
MUXCTRL(AV200_muxctrl_reg49, 0x120400C4, "TEST_CLK", "SDIO0_CDATA1", "GPIO6_5")
MUXCTRL(AV200_muxctrl_reg50, 0x120400C8, "GPIO6_6", "SDIO0_CDATA2")
MUXCTRL(AV200_muxctrl_reg51, 0x120400CC, "GPIO6_7", "SDIO0_CDATA3")
MUXCTRL(AV200_muxctrl_reg52, 0x120400D0, "GPIO4_4", "SDIO1_CARD_POWER_EN")
MUXCTRL(AV200_muxctrl_reg53, 0x120400D4, "GPIO7_0", "SDIO1_CARD_DETECT")
MUXCTRL(AV200_muxctrl_reg54, 0x120400D8, "GPIO7_1", "SDIO1_CWPR")
MUXCTRL(AV200_muxctrl_reg55, 0x120400DC, "GPIO7_2", "SDIO1_CCLK_OUT")
MUXCTRL(AV200_muxctrl_reg56, 0x120400E0, "GPIO7_3", "SDIO1_CCMD")
MUXCTRL(AV200_muxctrl_reg57, 0x120400E4, "GPIO7_4", "SDIO1_CDATA0")
MUXCTRL(AV200_muxctrl_reg58, 0x120400E8, "GPIO7_5", "SDIO1_CDATA1")
MUXCTRL(AV200_muxctrl_reg59, 0x120400EC, "GPIO7_6", "SDIO1_CDATA2")
MUXCTRL(AV200_muxctrl_reg60, 0x120400F0, "GPIO7_7", "SDIO1_CDATA3")
MUXCTRL(AV200_muxctrl_reg61, 0x120400F4, "GPIO4_5", "USB2_PWREN")
MUXCTRL(AV200_muxctrl_reg62, 0x120400F8, "GPIO4_6", "VO_CLK")
MUXCTRL(AV200_muxctrl_reg63, 0x120400FC, "GPIO8_0", "VO_DATA0")
MUXCTRL(AV200_muxctrl_reg64, 0x12040100, "GPIO8_1", "VO_DATA1")
MUXCTRL(AV200_muxctrl_reg65, 0x12040104, "GPIO8_2", "VO_DATA2")
MUXCTRL(AV200_muxctrl_reg66, 0x12040108, "GPIO8_3", "VO_DATA3")
MUXCTRL(AV200_muxctrl_reg67, 0x1204010C, "GPIO8_4", "VO_DATA4")
MUXCTRL(AV200_muxctrl_reg68, 0x12040110, "GPIO8_5", "VO_DATA5")
MUXCTRL(AV200_muxctrl_reg69, 0x12040114, "GPIO8_6", "VO_DATA6")
MUXCTRL(AV200_muxctrl_reg70, 0x12040118, "GPIO8_7", "VO_DATA7")
MUXCTRL(AV200_muxctrl_reg71, 0x1204011C, "GPIO9_0", "VO_DATA8")
MUXCTRL(AV200_muxctrl_reg72, 0x12040120, "GPIO9_1", "VO_DATA9", "reserved",
        "VO_VS")
MUXCTRL(AV200_muxctrl_reg73, 0x12040124, "GPIO9_2", "VO_DATA10", "reserved",
        "VO_HS")
MUXCTRL(AV200_muxctrl_reg74, 0x12040128, "GPIO9_3", "VO_DATA11", "reserved",
        "VO_DE")
MUXCTRL(AV200_muxctrl_reg75, 0x1204012C, "GPIO9_4", "VO_DATA12", "SPI3_SCLK",
        "I2C3_SCL")
MUXCTRL(AV200_muxctrl_reg76, 0x12040130, "GPIO9_5", "VO_DATA13", "SPI3_SDO",
        "I2C3_SDA")
MUXCTRL(AV200_muxctrl_reg77, 0x12040134, "GPIO9_6", "VO_DATA14", "SPI3_SDI")
MUXCTRL(AV200_muxctrl_reg78, 0x12040138, "GPIO9_7", "VO_DATA15", "SPI3_CSN")
MUXCTRL(AV200_muxctrl_reg79, 0x1204013C, "GPIO10_0", "VO_VS", "RGMII_TX_EN")
MUXCTRL(AV200_muxctrl_reg80, 0x12040140, "GPIO10_1", "VO_DATA18",
        "RGMII_TX_CLK", "RMII_CLK")
MUXCTRL(AV200_muxctrl_reg81, 0x12040144, "GPIO10_2", "VO_DATA16", "RGMII_TXD0")
MUXCTRL(AV200_muxctrl_reg82, 0x12040148, "GPIO10_3", "VO_DATA20", "RGMII_TXD1")
MUXCTRL(AV200_muxctrl_reg83, 0x1204014C, "GPIO10_4", "VO_DATA17", "RGMII_TXD2")
MUXCTRL(AV200_muxctrl_reg84, 0x12040150, "GPIO10_5", "VO_HS", "RGMII_TXD3")
MUXCTRL(AV200_muxctrl_reg85, 0x12040154, "GPIO10_6", "VO_DATA19",
        "RGMII_RX_CLK")
MUXCTRL(AV200_muxctrl_reg86, 0x12040158, "GPIO10_7", "VO_DATA23", "RGMII_RX_DV")
MUXCTRL(AV200_muxctrl_reg87, 0x1204015C, "GPIO11_0", "VO_DATA22", "RGMII_RXD0")
MUXCTRL(AV200_muxctrl_reg88, 0x12040160, "GPIO11_1", "SPI3_SCLK", "RGMII_RXD1",
        "I2C3_SCL")
MUXCTRL(AV200_muxctrl_reg89, 0x12040164, "GPIO11_2", "VO_DE", "RGMII_RXD2")
MUXCTRL(AV200_muxctrl_reg90, 0x12040168, "GPIO11_3", "VO_DATA21", "RGMII_RXD3")
MUXCTRL(AV200_muxctrl_reg91, 0x1204016C, "GPIO11_4", "reserved", "EPHY_RSTN")
MUXCTRL(AV200_muxctrl_reg92, 0x12040170, "GPIO11_5", "SPI3_SDI", "EPHY_CLK")
MUXCTRL(AV200_muxctrl_reg93, 0x12040174, "GPIO11_6", "SPI3_CSN", "MDCK")
MUXCTRL(AV200_muxctrl_reg94, 0x12040178, "GPIO11_7", "SPI3_SDO", "MDIO",
        "I2C3_SDA")
MUXCTRL(AV200_muxctrl_reg95, 0x1204017C, "GPIO12_0", "SENSOR0_CLK")
MUXCTRL(AV200_muxctrl_reg96, 0x12040180, "SENSOR0_RSTN", "GPIO12_1")
MUXCTRL(AV200_muxctrl_reg97, 0x12040184, "GPIO12_2", "SENSOR0_HS", "SENSOR1_HS")
MUXCTRL(AV200_muxctrl_reg98, 0x12040188, "GPIO12_3", "SENSOR0_VS", "SENSOR1_VS")
MUXCTRL(AV200_muxctrl_reg99, 0x1204018C, "GPIO12_4", "SPI0_SCLK", "I2C0_SCL",
        "SPI0_3WIRE_CLK")
MUXCTRL(AV200_muxctrl_reg100, 0x12040190, "GPIO12_5", "SPI0_SDO", "I2C0_SDA",
        "SPI0_3WIRE_DATA")
MUXCTRL(AV200_muxctrl_reg101, 0x12040194, "GPIO12_6", "SPI0_SDI")
MUXCTRL(AV200_muxctrl_reg102, 0x12040198, "GPIO12_7", "SPI0_CSN", "reserved",
        "SPI0_3WIRE_CSN")
MUXCTRL(AV200_muxctrl_reg118, 0x120401D8, "SAR_ADC_CH1", "GPIO16_1")
MUXCTRL(AV200_muxctrl_reg119, 0x120401DC, "SAR_ADC_CH2", "GPIO16_2")
MUXCTRL(AV200_muxctrl_reg120, 0x120401E0, "SAR_ADC_CH3", "GPIO16_3", "reserved",
        "TEMPER_DQ")

static const muxctrl_reg_t *AV200regs[] = {
    &AV200_muxctrl_reg0,
    &AV200_muxctrl_reg1,
    &AV200_muxctrl_reg2,
    &AV200_muxctrl_reg3,
    &AV200_muxctrl_reg4,
    &AV200_muxctrl_reg5,
    &AV200_muxctrl_reg6,
    &AV200_muxctrl_reg7,
    &AV200_muxctrl_reg8,
    &AV200_muxctrl_reg9,
    &AV200_muxctrl_reg10,
    &AV200_muxctrl_reg11,
    &AV200_muxctrl_reg12,
    &AV200_muxctrl_reg13,
    &AV200_muxctrl_reg14,
    &AV200_muxctrl_reg15,
    &AV200_muxctrl_reg16,
    &AV200_muxctrl_reg17,
    &AV200_muxctrl_reg18,
    &AV200_muxctrl_reg19,
    &AV200_muxctrl_reg20,
    &AV200_muxctrl_reg21,
    &AV200_muxctrl_reg22,
    &AV200_muxctrl_reg23,
    &AV200_muxctrl_reg24,
    &AV200_muxctrl_reg25,
    &AV200_muxctrl_reg26,
    &AV200_muxctrl_reg27,
    &AV200_muxctrl_reg28,
    &AV200_muxctrl_reg29,
    &AV200_muxctrl_reg30,
    &AV200_muxctrl_reg31,
    &AV200_muxctrl_reg32,
    &AV200_muxctrl_reg33,
    &AV200_muxctrl_reg34,
    &AV200_muxctrl_reg35,
    &AV200_muxctrl_reg36,
    &AV200_muxctrl_reg37,
    &AV200_muxctrl_reg38,
    &AV200_muxctrl_reg39,
    &AV200_muxctrl_reg40,
    &AV200_muxctrl_reg41,
    &AV200_muxctrl_reg42,
    &AV200_muxctrl_reg43,
    &AV200_muxctrl_reg44,
    &AV200_muxctrl_reg45,
    &AV200_muxctrl_reg46,
    &AV200_muxctrl_reg47,
    &AV200_muxctrl_reg48,
    &AV200_muxctrl_reg49,
    &AV200_muxctrl_reg50,
    &AV200_muxctrl_reg51,
    &AV200_muxctrl_reg52,
    &AV200_muxctrl_reg53,
    &AV200_muxctrl_reg54,
    &AV200_muxctrl_reg55,
    &AV200_muxctrl_reg56,
    &AV200_muxctrl_reg57,
    &AV200_muxctrl_reg58,
    &AV200_muxctrl_reg59,
    &AV200_muxctrl_reg60,
    &AV200_muxctrl_reg61,
    &AV200_muxctrl_reg62,
    &AV200_muxctrl_reg63,
    &AV200_muxctrl_reg64,
    &AV200_muxctrl_reg65,
    &AV200_muxctrl_reg66,
    &AV200_muxctrl_reg67,
    &AV200_muxctrl_reg68,
    &AV200_muxctrl_reg69,
    &AV200_muxctrl_reg70,
    &AV200_muxctrl_reg71,
    &AV200_muxctrl_reg72,
    &AV200_muxctrl_reg73,
    &AV200_muxctrl_reg74,
    &AV200_muxctrl_reg75,
    &AV200_muxctrl_reg76,
    &AV200_muxctrl_reg77,
    &AV200_muxctrl_reg78,
    &AV200_muxctrl_reg79,
    &AV200_muxctrl_reg80,
    &AV200_muxctrl_reg81,
    &AV200_muxctrl_reg82,
    &AV200_muxctrl_reg83,
    &AV200_muxctrl_reg84,
    &AV200_muxctrl_reg85,
    &AV200_muxctrl_reg86,
    &AV200_muxctrl_reg87,
    &AV200_muxctrl_reg88,
    &AV200_muxctrl_reg89,
    &AV200_muxctrl_reg90,
    &AV200_muxctrl_reg91,
    &AV200_muxctrl_reg92,
    &AV200_muxctrl_reg93,
    &AV200_muxctrl_reg94,
    &AV200_muxctrl_reg95,
    &AV200_muxctrl_reg96,
    &AV200_muxctrl_reg97,
    &AV200_muxctrl_reg98,
    &AV200_muxctrl_reg99,
    &AV200_muxctrl_reg100,
    &AV200_muxctrl_reg101,
    &AV200_muxctrl_reg102,
    &AV200_muxctrl_reg118,
    &AV200_muxctrl_reg119,
    &AV200_muxctrl_reg120,
    0,
};

MUXCTRL(CV300_muxctrl_reg0, 0x12040000, "GPIO1_7", "PWM3", "SVB_PWM")
MUXCTRL(CV300_muxctrl_reg1, 0x12040004, "GPIO6_5", "PWM0")
MUXCTRL(CV300_muxctrl_reg2, 0x12040008, "GPIO6_6", "PWM1")
MUXCTRL(CV300_muxctrl_reg3, 0x1204000C, "GPIO6_7", "PWM2")
MUXCTRL(CV300_muxctrl_reg4, 0x12040010, "GPIO6_2", "UART0_RXD")
MUXCTRL(CV300_muxctrl_reg5, 0x12040014, "GPIO6_3", "UART0_TXD")
MUXCTRL(CV300_muxctrl_reg6, 0x12040018, "GPIO6_1", "SHUTTER_TRIG")
MUXCTRL(CV300_muxctrl_reg7, 0x1204001C, "GPIO6_0", "FLASH_TRIG")
MUXCTRL(CV300_muxctrl_reg8, 0x12040020, "GPIO3_6", "I2C1_SDA")
MUXCTRL(CV300_muxctrl_reg9, 0x12040024, "GPIO3_7", "I2C1_SCL")
MUXCTRL(CV300_muxctrl_reg10, 0x12040028, "GPIO0_5", "SPI0_SDI")
MUXCTRL(CV300_muxctrl_reg11, 0x1204002C, "GPIO0_4", "SPI0_SDO",
        "SPI_3LINE_SDATA", "I2C0_SDA")
MUXCTRL(CV300_muxctrl_reg12, 0x12040030, "GPIO8_3", "SPI0_SCLK",
        "SPI_3LINE_SCLK", "I2C0_SCL")
MUXCTRL(CV300_muxctrl_reg13, 0x12040034, "GPIO0_6", "SPI0_CSN", "SPI_3LINE_CSN")
MUXCTRL(CV300_muxctrl_reg14, 0x12040038, "GPIO0_7", "SENSOR_RSTN")
MUXCTRL(CV300_muxctrl_reg15, 0x1204003C, "GPIO6_4", "SENSOR_CLK")
MUXCTRL(CV300_muxctrl_reg16, 0x12040040, "GPIO1_0", "VI_DATA13", "VOU656_CLK",
        "LCD_CLK", "I2S_MCLK", "SDIO2_CCLK_OUT")
MUXCTRL(CV300_muxctrl_reg17, 0x12040044, "GPIO1_1", "VI_DATA10", "VOU656_DATA3",
        "LCD_DATA1", "I2S_SD_TX", "SDIO2_CDATA3")
MUXCTRL(CV300_muxctrl_reg18, 0x12040048, "GPIO1_2", "VI_DATA12", "VOU656_DATA7",
        "LCD_DATA3", "I2S_BCLK_TX", "SDIO2_CDATA1")
MUXCTRL(CV300_muxctrl_reg19, 0x1204004C, "GPIO1_3", "VI_DATA11", "VOU656_DATA2",
        "LCD_DATA2", "I2S_WS_TX", "SDIO2_CDATA2")
MUXCTRL(CV300_muxctrl_reg20, 0x12040050, "GPIO1_4", "VI_DATA9", "VOU656_DATA6",
        "LCD_DATA4")
MUXCTRL(CV300_muxctrl_reg21, 0x12040054, "GPIO1_5", "VI_DATA14", "VOU656_DATA5",
        "LCD_DATA5", "reserved", "SDIO2_CDATA0")
MUXCTRL(CV300_muxctrl_reg22, 0x12040058, "GPIO1_6", "VI_DATA15", "VOU656_DATA4",
        "LCD_DATA0", "I2S_SD_RX", "SDIO2_CCMD")
MUXCTRL(CV300_muxctrl_reg23, 0x1204005C, "GPIO3_4", "VI_VS", "VOU656_DATA1",
        "LCD_HSYNC", "UART2_RXD")
MUXCTRL(CV300_muxctrl_reg24, 0x12040060, "GPIO3_5", "VI_HS", "VOU656_DATA0",
        "LCD_VSYNC", "UART2_TXD")
MUXCTRL(CV300_muxctrl_reg25, 0x12040064, "GPIO7_7", "USB_PWREN", "reserved",
        "LCD_DE")
MUXCTRL(CV300_muxctrl_reg26, 0x12040068, "GPIO4_1", "SDIO0_CARD_DETECT")
MUXCTRL(CV300_muxctrl_reg27, 0x1204006C, "GPIO4_0", "SDIO0_CARD_POWER_EN",
        "JTAG_TCK")
MUXCTRL(CV300_muxctrl_reg28, 0x12040070, "GPIO4_4", "SDIO0_CDATA0")
MUXCTRL(CV300_muxctrl_reg29, 0x12040074, "GPIO4_5", "SDIO0_CDATA1", "JTAG_TMS")
MUXCTRL(CV300_muxctrl_reg30, 0x12040078, "GPIO4_3", "SDIO0_CCMD")
MUXCTRL(CV300_muxctrl_reg31, 0x1204007C, "GPIO4_2", "SDIO0_CCLK_OUT",
        "JTAG_TRSTN")
MUXCTRL(CV300_muxctrl_reg32, 0x12040080, "GPIO4_7", "SDIO0_CDATA3", "JTAG_TDI")
MUXCTRL(CV300_muxctrl_reg33, 0x12040084, "GPIO4_6", "SDIO0_CDATA2", "JTAG_TDO")
MUXCTRL(CV300_muxctrl_reg34, 0x12040088, "GPIO3_3", "UART1_TXD")
MUXCTRL(CV300_muxctrl_reg35, 0x1204008C, "GPIO3_2", "UART1_CTSN")
MUXCTRL(CV300_muxctrl_reg36, 0x12040090, "GPIO3_1", "UART1_RXD")
MUXCTRL(CV300_muxctrl_reg37, 0x12040094, "GPIO3_0", "UART1_RTSN")
MUXCTRL(CV300_muxctrl_reg38, 0x12040098, "GPIO2_5", "RMII_RXD0", "SDIO1_CDATA2",
        "LCD_HSYNC")
MUXCTRL(CV300_muxctrl_reg39, 0x1204009C, "GPIO2_4", "RMII_RX_DV",
        "SDIO1_CARD_POWER_EN", "LCD_DATA0")
MUXCTRL(CV300_muxctrl_reg40, 0x120400A0, "GPIO2_6", "RMII_RXD1", "SDIO1_CCMD",
        "LCD_DATA5")
MUXCTRL(CV300_muxctrl_reg41, 0x120400A4, "GPIO5_6", "MDCK")
MUXCTRL(CV300_muxctrl_reg42, 0x120400A8, "GPIO5_7", "MDIO", "SDIO1_CARD_DETECT",
        "LCD_DATA1")
MUXCTRL(CV300_muxctrl_reg43, 0x120400AC, "GPIO2_3", "RMII_TXD1", "SDIO1_CDATA1",
        "LCD_DATA2")
MUXCTRL(CV300_muxctrl_reg44, 0x120400B0, "GPIO2_2", "RMII_TXD0", "SDIO1_CDATA0",
        "LCD_DATA3", "TEST_CLK")
MUXCTRL(CV300_muxctrl_reg45, 0x120400B4, "GPIO2_1", "RMII_TX_EN",
        "SDIO1_CDATA3", "LCD_DATA4")
MUXCTRL(CV300_muxctrl_reg46, 0x120400B8, "GPIO2_0", "RMII_CLK",
        "SDIO1_CCLK_OUT", "LCD_CLK")
MUXCTRL(CV300_muxctrl_reg47, 0x120400BC, "GPIO5_5", "EPHY_CLK", "reserved",
        "LCD_VSYNC")
MUXCTRL(CV300_muxctrl_reg48, 0x120400C0, "GPIO2_7", "EPHY_RSTN", "reserved",
        "LCD_DE")
MUXCTRL(CV300_muxctrl_reg49, 0x120400C4, "GPIO5_4", "SPI1_CSN1", "UART2_RXD",
        "JTAG_TDI", "I2S_SD_TX")
MUXCTRL(CV300_muxctrl_reg50, 0x120400C8, "GPIO5_3", "SPI1_CSN0", "UART2_TXD",
        "JTAG_TMS", "I2S_WS_TX")
MUXCTRL(CV300_muxctrl_reg51, 0x120400CC, "GPIO5_1", "SPI1_SDO", "reserved",
        "JTAG_TCK", "I2S_BCLK_TX")
MUXCTRL(CV300_muxctrl_reg52, 0x120400D0, "GPIO5_2", "SPI1_SDI", "reserved",
        "JTAG_TDO", "I2S_MCLK")
MUXCTRL(CV300_muxctrl_reg53, 0x120400D4, "GPIO5_0", "SPI1_SCLK", "reserved",
        "JTAG_TRSTN", "I2S_SD_RX")
MUXCTRL(CV300_muxctrl_reg55, 0x120400DC, "PWR_WAKEUP", "GPIO7_1")
MUXCTRL(CV300_muxctrl_reg56, 0x120400E0, "PWR_SEQ0", "GPIO7_2")
MUXCTRL(CV300_muxctrl_reg57, 0x120400E4, "PWR_SEQ1", "GPIO7_3")
MUXCTRL(CV300_muxctrl_reg58, 0x120400E8, "PWR_SEQ2", "GPIO7_4")
MUXCTRL(CV300_muxctrl_reg59, 0x120400EC, "PWR_EN_OUT", "GPIO7_5")
MUXCTRL(CV300_muxctrl_reg60, 0x120400F0, "PWR_BUTTON", "GPIO7_6")
MUXCTRL(CV300_muxctrl_reg61, 0x120400F4, "GPIO0_0", "IR_IN")
MUXCTRL(CV300_muxctrl_reg62, 0x120400F8, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(CV300_muxctrl_reg63, 0x120400FC, "GPIO8_0", "SAR_ADC_CH0")
MUXCTRL(CV300_muxctrl_reg64, 0x12040100, "GPIO8_1", "SAR_ADC_CH1")
MUXCTRL(CV300_muxctrl_reg65, 0x12040104, "GPIO8_2", "SAR_ADC_CH2")

static const muxctrl_reg_t *CV300regs[] = {
    &CV300_muxctrl_reg0,  &CV300_muxctrl_reg1,  &CV300_muxctrl_reg2,
    &CV300_muxctrl_reg3,  &CV300_muxctrl_reg4,  &CV300_muxctrl_reg5,
    &CV300_muxctrl_reg6,  &CV300_muxctrl_reg7,  &CV300_muxctrl_reg8,
    &CV300_muxctrl_reg9,  &CV300_muxctrl_reg10, &CV300_muxctrl_reg11,
    &CV300_muxctrl_reg12, &CV300_muxctrl_reg13, &CV300_muxctrl_reg14,
    &CV300_muxctrl_reg15, &CV300_muxctrl_reg16, &CV300_muxctrl_reg17,
    &CV300_muxctrl_reg18, &CV300_muxctrl_reg19, &CV300_muxctrl_reg20,
    &CV300_muxctrl_reg21, &CV300_muxctrl_reg22, &CV300_muxctrl_reg23,
    &CV300_muxctrl_reg24, &CV300_muxctrl_reg25, &CV300_muxctrl_reg26,
    &CV300_muxctrl_reg27, &CV300_muxctrl_reg28, &CV300_muxctrl_reg29,
    &CV300_muxctrl_reg30, &CV300_muxctrl_reg31, &CV300_muxctrl_reg32,
    &CV300_muxctrl_reg33, &CV300_muxctrl_reg34, &CV300_muxctrl_reg35,
    &CV300_muxctrl_reg36, &CV300_muxctrl_reg37, &CV300_muxctrl_reg38,
    &CV300_muxctrl_reg39, &CV300_muxctrl_reg40, &CV300_muxctrl_reg41,
    &CV300_muxctrl_reg42, &CV300_muxctrl_reg43, &CV300_muxctrl_reg44,
    &CV300_muxctrl_reg45, &CV300_muxctrl_reg46, &CV300_muxctrl_reg47,
    &CV300_muxctrl_reg48, &CV300_muxctrl_reg49, &CV300_muxctrl_reg50,
    &CV300_muxctrl_reg51, &CV300_muxctrl_reg52, &CV300_muxctrl_reg53,
    &CV300_muxctrl_reg55, &CV300_muxctrl_reg56, &CV300_muxctrl_reg57,
    &CV300_muxctrl_reg58, &CV300_muxctrl_reg59, &CV300_muxctrl_reg60,
    &CV300_muxctrl_reg61, &CV300_muxctrl_reg62, &CV300_muxctrl_reg63,
    &CV300_muxctrl_reg64, &CV300_muxctrl_reg65, 0,
};

MUXCTRL(CV500_iocfg_reg0, 0x10FF0000, "EMMC_CLK", "SFC_CLK", "SFC_BOOT_MODE")
MUXCTRL(CV500_iocfg_reg1, 0x10FF0004, "EMMC_CMD", "SFC_HOLD_IO3")
MUXCTRL(CV500_iocfg_reg2, 0x10FF0008, "EMMC_DATA0", "SFC_WP_IO2")
MUXCTRL(CV500_iocfg_reg3, 0x10FF000C, "EMMC_DATA1", "SFC_MISO_IO1")
MUXCTRL(CV500_iocfg_reg4, 0x10FF0010, "EMMC_DATA2", "SFC_CSN", "GPIO0_7")
MUXCTRL(CV500_iocfg_reg5, 0x10FF0014, "EMMC_DATA3", "SFC_MOSI_IO0")
MUXCTRL(CV500_iocfg_reg6, 0x10FF0018, "EMMC_RST_N", "SYS_RSTN_OUT", "GPIO10_5")
MUXCTRL(CV500_iocfg_reg7, 0x10FF001C, "GPIO1_0", "SDIO0_CARD_POWER_EN",
        "JTAG_TCK", "USBPHY_TEST_OBS0")
MUXCTRL(CV500_iocfg_reg8, 0x10FF0020, "GPIO1_1", "SDIO0_CARD_DETECT",
        "reserved", "USBPHY_TEST_OBS1")
MUXCTRL(CV500_iocfg_reg9, 0x10FF0024, "GPIO1_2", "SDIO0_CCLK_OUT", "JTAG_TRSTN",
        "USBPHY_TEST_OBS2")
MUXCTRL(CV500_iocfg_reg10, 0x10FF0028, "GPIO1_3", "SDIO0_CCMD", "reserved",
        "USBPHY_TEST_OBS3")
MUXCTRL(CV500_iocfg_reg11, 0x10FF002C, "GPIO1_4", "SDIO0_CDATA0", "reserved",
        "USBPHY_TEST_OBS4")
MUXCTRL(CV500_iocfg_reg12, 0x10FF0030, "GPIO1_5", "SDIO0_CDATA1", "JTAG_TMS",
        "USBPHY_TEST_OBS5")
MUXCTRL(CV500_iocfg_reg13, 0x10FF0034, "GPIO1_6", "SDIO0_CDATA2", "JTAG_TDO",
        "USBPHY_TEST_OBS6")
MUXCTRL(CV500_iocfg_reg14, 0x10FF0038, "GPIO1_7", "SDIO0_CDATA3", "JTAG_TDI",
        "USBPHY_TEST_OBS7")
MUXCTRL(CV500_iocfg_reg15, 0x10FF003C, "GPIO2_0", "USB_OVRCUR")
MUXCTRL(CV500_iocfg_reg16, 0x10FF0040, "GPIO2_1", "USB_VBUS")
MUXCTRL(CV500_iocfg_reg17, 0x10FF0044, "GPIO2_2", "USB_PWREN")
MUXCTRL(CV500_iocfg_reg22, 0x114F0010, "reserved", "VI_DATA8")
MUXCTRL(CV500_iocfg_reg23, 0x114F0014, "reserved", "VI_DATA9")
MUXCTRL(CV500_iocfg_reg24, 0x114F0018, "MIPI_RX_D2N", "VI_DATA15")
MUXCTRL(CV500_iocfg_reg25, 0x114F001C, "MIPI_RX_D2P", "VI_DATA14")
MUXCTRL(CV500_iocfg_reg26, 0x114F0020, "MIPI_RX_D3N", "VI_DATA10")
MUXCTRL(CV500_iocfg_reg27, 0x114F0024, "MIPI_RX_D3P", "VI_DATA11")
MUXCTRL(CV500_iocfg_reg28, 0x114F0028, "MIPI_RX_CK0N", "VI_DATA13")
MUXCTRL(CV500_iocfg_reg29, 0x114F002C, "MIPI_RX_CK0P", "VI_DATA12")
MUXCTRL(CV500_iocfg_reg30, 0x114F0030, "MIPI_RX_D0N")
MUXCTRL(CV500_iocfg_reg31, 0x114F0034, "MIPI_RX_D0P")
MUXCTRL(CV500_iocfg_reg32, 0x114F0038, "MIPI_RX_D1N")
MUXCTRL(CV500_iocfg_reg33, 0x114F003C, "MIPI_RX_D1P")
MUXCTRL(CV500_iocfg_reg34, 0x114F0040, "GPIO3_0", "VI_DATA0", "VOU656_DATA0",
        "I2C5_SCL")
MUXCTRL(CV500_iocfg_reg35, 0x114F0044, "GPIO3_1", "VI_DATA1", "VOU656_DATA1",
        "I2C5_SDA")
MUXCTRL(CV500_iocfg_reg36, 0x114F0048, "GPIO3_2", "VI_DATA2", "VOU656_DATA2",
        "I2C6_SCL")
MUXCTRL(CV500_iocfg_reg37, 0x114F004C, "GPIO3_3", "VI_DATA3", "VOU656_DATA3",
        "I2C6_SDA")
MUXCTRL(CV500_iocfg_reg38, 0x114F0050, "GPIO3_4", "VI_DATA4", "VOU656_DATA4",
        "UART2_RTSN", "SPI2_SCLK")
MUXCTRL(CV500_iocfg_reg39, 0x114F0054, "GPIO3_5", "VI_DATA5", "VOU656_DATA5",
        "UART2_CTSN", "SPI2_SDO")
MUXCTRL(CV500_iocfg_reg40, 0x114F0058, "GPIO3_6", "VI_DATA6", "VOU656_DATA6",
        "UART2_RXD", "SPI2_SDI")
MUXCTRL(CV500_iocfg_reg41, 0x114F005C, "GPIO3_7", "VI_DATA7", "VOU656_DATA7",
        "UART2_TXD", "SPI2_CSN")
MUXCTRL(CV500_iocfg_reg42, 0x114F0060, "GPIO4_6", "VI_VS", "reserved",
        "FLASH_TRIG", "SENSOR_VS")
MUXCTRL(CV500_iocfg_reg43, 0x114F0064, "GPIO4_7", "VI_HS", "reserved",
        "SHUTTER_TRIG", "SENSOR_HS")
MUXCTRL(CV500_iocfg_reg44, 0x114F0068, "GPIO2_3", "VI_CLK", "VOU656_CLK")
MUXCTRL(CV500_iocfg_reg45, 0x114F006C, "GPIO4_0", "SENSOR0_CLK")
MUXCTRL(CV500_iocfg_reg46, 0x114F0070, "GPIO4_1", "SENSOR0_RSTN", "BOOT_SEL1")
MUXCTRL(CV500_iocfg_reg47, 0x114F0074, "GPIO4_2", "SPI0_SCLK", "I2C0_SCL",
        "SPI_3LINE_SCLK")
MUXCTRL(CV500_iocfg_reg48, 0x114F0078, "GPIO4_3", "SPI0_SDO", "I2C0_SDA",
        "SPI_3LINE_SDATA")
MUXCTRL(CV500_iocfg_reg49, 0x114F007C, "GPIO4_4", "SPI0_SDI", "I2C1_SDA",
        "reserved", "SENSOR_VS")
MUXCTRL(CV500_iocfg_reg50, 0x114F0080, "GPIO4_5", "SPI0_CSN", "I2C1_SCL",
        "SPI_3LINE_CSN", "SENSOR_HS")
MUXCTRL(CV500_iocfg_reg51, 0x111F0000, "GPIO5_0", "UART1_RTSN", "UART4_RXD")
MUXCTRL(CV500_iocfg_reg52, 0x111F0004, "GPIO5_1", "UART1_CTSN", "UART4_TXD")
MUXCTRL(CV500_iocfg_reg53, 0x111F0008, "GPIO5_2", "UART1_RXD")
MUXCTRL(CV500_iocfg_reg54, 0x111F000C, "GPIO5_3", "UART1_TXD")
MUXCTRL(CV500_iocfg_reg55, 0x111F0010, "GPIO5_4", "UART0_RXD")
MUXCTRL(CV500_iocfg_reg56, 0x111F0014, "GPIO5_5", "UART0_TXD")
MUXCTRL(CV500_iocfg_reg57, 0x111F0018, "GPIO5_6", "I2C2_SDA")
MUXCTRL(CV500_iocfg_reg58, 0x111F001C, "GPIO5_7", "I2C2_SCL")
MUXCTRL(CV500_iocfg_reg59, 0x111F0020, "TEST_MODE")
MUXCTRL(CV500_iocfg_reg60, 0x111F0024, "GPIO6_6", "PWM0")
MUXCTRL(CV500_iocfg_reg61, 0x111F0028, "GPIO6_7", "PWM1")
MUXCTRL(CV500_iocfg_reg62, 0x111F002C, "SVB_PWM", "GPIO10_2")
MUXCTRL(CV500_iocfg_reg63, 0x111F0030, "LSADC_CH0", "GPIO10_3")
MUXCTRL(CV500_iocfg_reg64, 0x111F0034, "LSADC_CH1", "GPIO10_4")
MUXCTRL(CV500_iocfg_reg65, 0x112F0000, "GPIO10_6", "I2C7_SCL")
MUXCTRL(CV500_iocfg_reg66, 0x112F0004, "GPIO10_7", "I2C7_SDA", "RMII_CLK")
MUXCTRL(CV500_iocfg_reg67, 0x112F0008, "GPIO6_0", "SDIO1_CCLK_OUT",
        "RMII_RX_DV")
MUXCTRL(CV500_iocfg_reg68, 0x112F000C, "GPIO6_1", "SDIO1_CCMD", "EPHY_CLK")
MUXCTRL(CV500_iocfg_reg69, 0x112F0010, "GPIO6_2", "SDIO1_CDATA0", "MDCK")
MUXCTRL(CV500_iocfg_reg70, 0x112F0014, "GPIO6_3", "SDIO1_CDATA1", "MDIO")
MUXCTRL(CV500_iocfg_reg71, 0x112F0018, "GPIO6_4", "SDIO1_CDATA2", "RMII_TX_EN")
MUXCTRL(CV500_iocfg_reg72, 0x112F001C, "GPIO6_5", "SDIO1_CDATA3", "EPHY_RSTN")
MUXCTRL(CV500_iocfg_reg73, 0x112F0020, "JTAG_TRSTN", "SPI1_SCLK", "RMII_TXD1",
        "I2S_MCLK", "GPIO8_0")
MUXCTRL(CV500_iocfg_reg74, 0x112F0024, "JTAG_TCK", "SPI1_SDO", "RMII_RXD1",
        "I2S_BCLK_TX", "GPIO8_1")
MUXCTRL(CV500_iocfg_reg75, 0x112F0028, "JTAG_TMS", "SPI1_CSN0", "RMII_TXD0",
        "I2S_WS_TX", "GPIO8_2")
MUXCTRL(CV500_iocfg_reg76, 0x112F002C, "JTAG_TDO", "SPI1_SDI", "RMII_RXD0",
        "I2S_SD_TX", "GPIO8_3")
MUXCTRL(CV500_iocfg_reg77, 0x112F0030, "JTAG_TDI", "SPI1_CSN1", "LCD_DATA23",
        "I2S_SD_RX", "GPIO8_4")
MUXCTRL(CV500_iocfg_reg78, 0x112F0034, "GPIO0_6", "reserved", "LCD_CLK",
        "VOU1120_CLK/VOU656_CLK")
MUXCTRL(CV500_iocfg_reg79, 0x112F0038, "GPIO8_5", "MDIO", "LCD_DATA5",
        "VOU1120_DATA2/VOU656_DATA2")
MUXCTRL(CV500_iocfg_reg80, 0x112F003C, "GPIO8_6", "MDCK", "LCD_DATA4",
        "VOU1120_DATA3/VOU656_DATA3", "BOOT_SEL0")
MUXCTRL(CV500_iocfg_reg81, 0x112F0040, "TEST_CLK", "RMII_TXD1", "LCD_DATA1",
        "VOU1120_DATA6/VOU656_DATA6", "GPIO8_7")
MUXCTRL(CV500_iocfg_reg82, 0x112F0044, "GPIO7_0", "RMII_TX_EN", "LCD_DATA2",
        "VOU1120_DATA5/VOU656_DATA5")
MUXCTRL(CV500_iocfg_reg83, 0x112F0048, "GPIO7_1", "RMII_TXD0", "LCD_DATA0",
        "VOU1120_DATA7/VOU656_DATA7")
MUXCTRL(CV500_iocfg_reg84, 0x112F004C, "GPIO7_2", "RMII_CLK", "LCD_HSYNC")
MUXCTRL(CV500_iocfg_reg85, 0x112F0050, "GPIO7_3", "RMII_RX_DV", "LCD_DATA6",
        "VOU1120_DATA1/VOU656_DATA1")
MUXCTRL(CV500_iocfg_reg86, 0x112F0054, "GPIO7_4", "RMII_RXD1", "LCD_VSYNC")
MUXCTRL(CV500_iocfg_reg87, 0x112F0058, "GPIO7_5", "RMII_RXD0", "LCD_DE")
MUXCTRL(CV500_iocfg_reg88, 0x112F005C, "GPIO7_6", "EPHY_RSTN", "LCD_DATA3",
        "VOU1120_DATA4/VOU656_DATA4", "SFC_DEVICE_MODE")
MUXCTRL(CV500_iocfg_reg89, 0x112F0060, "GPIO7_7", "EPHY_CLK", "LCD_DATA7",
        "VOU1120_DATA0/VOU656_DATA0")
MUXCTRL(CV500_iocfg_reg90, 0x112F0064, "DSI_D3P", "GPIO9_0", "LCD_DATA16",
        "SHUTTER_TRIG", "LCD_DATA5")
MUXCTRL(CV500_iocfg_reg91, 0x112F0068, "DSI_D3N", "GPIO9_1", "LCD_DATA17",
        "FLASH_TRIG", "LCD_CLK")
MUXCTRL(CV500_iocfg_reg92, 0x112F006C, "DSI_D2N", "GPIO9_2", "LCD_DATA14",
        "VOU1120_DATA9", "LCD_DATA3")
MUXCTRL(CV500_iocfg_reg93, 0x112F0070, "DSI_D2P", "GPIO9_3", "LCD_DATA15",
        "VOU1120_DATA8", "LCD_DATA4")
MUXCTRL(CV500_iocfg_reg94, 0x112F0074, "DSI_CKP", "GPIO9_4", "LCD_DATA12",
        "VOU1120_DATA11", "LCD_DATA1")
MUXCTRL(CV500_iocfg_reg95, 0x112F0078, "DSI_CKN", "GPIO9_5", "LCD_DATA13",
        "VOU1120_DATA10", "LCD_DATA2")
MUXCTRL(CV500_iocfg_reg96, 0x112F007C, "DSI_D1N", "GPIO9_6", "LCD_DATA10",
        "VOU1120_DATA13", "LCD_HSYNC")
MUXCTRL(CV500_iocfg_reg97, 0x112F0080, "DSI_D1P", "GPIO9_7", "LCD_DATA11",
        "VOU1120_DATA12", "LCD_DATA0")
MUXCTRL(CV500_iocfg_reg98, 0x112F0084, "DSI_D0P", "GPIO10_0", "LCD_DATA8",
        "VOU1120_DATA15", "LCD_DE")
MUXCTRL(CV500_iocfg_reg99, 0x112F0088, "DSI_D0N", "GPIO10_1", "LCD_DATA9",
        "VOU1120_DATA14", "LCD_VSYNC")
MUXCTRL(CV500_iocfg_reg100, 0x112F008C, "GPIO0_1", "I2C3_SDA", "LCD_DATA20")
MUXCTRL(CV500_iocfg_reg101, 0x112F0090, "GPIO0_2", "I2C3_SCL", "LCD_DATA19")
MUXCTRL(CV500_iocfg_reg102, 0x112F0094, "GPIO0_3", "IR_IN", "LCD_DATA18")
MUXCTRL(CV500_iocfg_reg103, 0x112F0098, "GPIO0_4", "reserved", "LCD_DATA21")
MUXCTRL(CV500_iocfg_reg104, 0x112F009C, "GPIO0_5", "reserved", "LCD_DATA22")
MUXCTRL(CV500_iocfg_reg105, 0x112F00A0, "GPIO0_0", "UPDATE_MODE")
MUXCTRL(CV500_iocfg_reg107, 0x112F00A8, "PWR_WAKEUP", "GPIO11_0")
MUXCTRL(CV500_iocfg_reg108, 0x112F00AC, "PWR_SEQ0", "GPIO11_1")

static const muxctrl_reg_t *CV500regs[] = {
    &CV500_iocfg_reg0,   &CV500_iocfg_reg1,   &CV500_iocfg_reg2,
    &CV500_iocfg_reg3,   &CV500_iocfg_reg4,   &CV500_iocfg_reg5,
    &CV500_iocfg_reg6,   &CV500_iocfg_reg7,   &CV500_iocfg_reg8,
    &CV500_iocfg_reg9,   &CV500_iocfg_reg10,  &CV500_iocfg_reg11,
    &CV500_iocfg_reg12,  &CV500_iocfg_reg13,  &CV500_iocfg_reg14,
    &CV500_iocfg_reg15,  &CV500_iocfg_reg16,  &CV500_iocfg_reg17,
    &CV500_iocfg_reg22,  &CV500_iocfg_reg23,  &CV500_iocfg_reg24,
    &CV500_iocfg_reg25,  &CV500_iocfg_reg26,  &CV500_iocfg_reg27,
    &CV500_iocfg_reg28,  &CV500_iocfg_reg29,  &CV500_iocfg_reg30,
    &CV500_iocfg_reg31,  &CV500_iocfg_reg32,  &CV500_iocfg_reg33,
    &CV500_iocfg_reg34,  &CV500_iocfg_reg35,  &CV500_iocfg_reg36,
    &CV500_iocfg_reg37,  &CV500_iocfg_reg38,  &CV500_iocfg_reg39,
    &CV500_iocfg_reg40,  &CV500_iocfg_reg41,  &CV500_iocfg_reg42,
    &CV500_iocfg_reg43,  &CV500_iocfg_reg44,  &CV500_iocfg_reg45,
    &CV500_iocfg_reg46,  &CV500_iocfg_reg47,  &CV500_iocfg_reg48,
    &CV500_iocfg_reg49,  &CV500_iocfg_reg50,  &CV500_iocfg_reg51,
    &CV500_iocfg_reg52,  &CV500_iocfg_reg53,  &CV500_iocfg_reg54,
    &CV500_iocfg_reg55,  &CV500_iocfg_reg56,  &CV500_iocfg_reg57,
    &CV500_iocfg_reg58,  &CV500_iocfg_reg59,  &CV500_iocfg_reg60,
    &CV500_iocfg_reg61,  &CV500_iocfg_reg62,  &CV500_iocfg_reg63,
    &CV500_iocfg_reg64,  &CV500_iocfg_reg65,  &CV500_iocfg_reg66,
    &CV500_iocfg_reg67,  &CV500_iocfg_reg68,  &CV500_iocfg_reg69,
    &CV500_iocfg_reg70,  &CV500_iocfg_reg71,  &CV500_iocfg_reg72,
    &CV500_iocfg_reg73,  &CV500_iocfg_reg74,  &CV500_iocfg_reg75,
    &CV500_iocfg_reg76,  &CV500_iocfg_reg77,  &CV500_iocfg_reg78,
    &CV500_iocfg_reg79,  &CV500_iocfg_reg80,  &CV500_iocfg_reg81,
    &CV500_iocfg_reg82,  &CV500_iocfg_reg83,  &CV500_iocfg_reg84,
    &CV500_iocfg_reg85,  &CV500_iocfg_reg86,  &CV500_iocfg_reg87,
    &CV500_iocfg_reg88,  &CV500_iocfg_reg89,  &CV500_iocfg_reg90,
    &CV500_iocfg_reg91,  &CV500_iocfg_reg92,  &CV500_iocfg_reg93,
    &CV500_iocfg_reg94,  &CV500_iocfg_reg95,  &CV500_iocfg_reg96,
    &CV500_iocfg_reg97,  &CV500_iocfg_reg98,  &CV500_iocfg_reg99,
    &CV500_iocfg_reg100, &CV500_iocfg_reg101, &CV500_iocfg_reg102,
    &CV500_iocfg_reg103, &CV500_iocfg_reg104, &CV500_iocfg_reg105,
    &CV500_iocfg_reg107, &CV500_iocfg_reg108, 0,
};

MUXCTRL(DV300_iocfg_reg0, 0x10FF0000, "EMMC_CLK", "SFC_CLK", "SFC_BOOT_MODE")
MUXCTRL(DV300_iocfg_reg1, 0x10FF0004, "EMMC_CMD", "SFC_HOLD_IO3")
MUXCTRL(DV300_iocfg_reg2, 0x10FF0008, "EMMC_DATA0", "SFC_WP_IO2")
MUXCTRL(DV300_iocfg_reg3, 0x10FF000C, "EMMC_DATA1", "SFC_MISO_IO1")
MUXCTRL(DV300_iocfg_reg4, 0x10FF0010, "EMMC_DATA2", "SFC_CSN", "GPIO0_7")
MUXCTRL(DV300_iocfg_reg5, 0x10FF0014, "EMMC_DATA3", "SFC_MOSI_IO0")
MUXCTRL(DV300_iocfg_reg6, 0x10FF0018, "EMMC_RST_N", "SYS_RSTN_OUT", "GPIO10_5")
MUXCTRL(DV300_iocfg_reg7, 0x10FF001C, "GPIO1_0", "SDIO0_CARD_POWER_EN",
        "JTAG_TCK", "USBPHY_TEST_OBS0")
MUXCTRL(DV300_iocfg_reg8, 0x10FF0020, "GPIO1_1", "SDIO0_CARD_DETECT",
        "reserved", "USBPHY_TEST_OBS1")
MUXCTRL(DV300_iocfg_reg9, 0x10FF0024, "GPIO1_2", "SDIO0_CCLK_OUT", "JTAG_TRSTN",
        "USBPHY_TEST_OBS2")
MUXCTRL(DV300_iocfg_reg10, 0x10FF0028, "GPIO1_3", "SDIO0_CCMD", "reserved",
        "USBPHY_TEST_OBS3")
MUXCTRL(DV300_iocfg_reg11, 0x10FF002C, "GPIO1_4", "SDIO0_CDATA0", "reserved",
        "USBPHY_TEST_OBS4")
MUXCTRL(DV300_iocfg_reg12, 0x10FF0030, "GPIO1_5", "SDIO0_CDATA1", "JTAG_TMS",
        "USBPHY_TEST_OBS5")
MUXCTRL(DV300_iocfg_reg13, 0x10FF0034, "GPIO1_6", "SDIO0_CDATA2", "JTAG_TDO",
        "USBPHY_TEST_OBS6")
MUXCTRL(DV300_iocfg_reg14, 0x10FF0038, "GPIO1_7", "SDIO0_CDATA3", "JTAG_TDI",
        "USBPHY_TEST_OBS7")
MUXCTRL(DV300_iocfg_reg15, 0x10FF003C, "GPIO2_0", "USB_OVRCUR")
MUXCTRL(DV300_iocfg_reg16, 0x10FF0040, "GPIO2_1", "USB_VBUS")
MUXCTRL(DV300_iocfg_reg17, 0x10FF0044, "GPIO2_2", "USB_PWREN")
MUXCTRL(DV300_iocfg_reg18, 0x114F0000, "GPIO2_4", "HDMI_HOTPLUG", "UART3_RXD")
MUXCTRL(DV300_iocfg_reg19, 0x114F0004, "GPIO2_5", "HDMI_CEC", "UART3_TXD")
MUXCTRL(DV300_iocfg_reg20, 0x114F0008, "GPIO2_6", "HDMI_SDA", "UART3_RTSN",
        "I2C4_SDA", "FLASH_TRIG")
MUXCTRL(DV300_iocfg_reg21, 0x114F000C, "GPIO2_7", "HDMI_SCL", "UART3_CTSN",
        "I2C4_SCL", "SHUTTER_TRIG")
MUXCTRL(DV300_iocfg_reg22, 0x114F0010, "MIPI_RX_CK1N", "VI_DATA8")
MUXCTRL(DV300_iocfg_reg23, 0x114F0014, "MIPI_RX_CK1P", "VI_DATA9")
MUXCTRL(DV300_iocfg_reg24, 0x114F0018, "MIPI_RX_D2N", "VI_DATA15")
MUXCTRL(DV300_iocfg_reg25, 0x114F001C, "MIPI_RX_D2P", "VI_DATA14")
MUXCTRL(DV300_iocfg_reg26, 0x114F0020, "MIPI_RX_D3N", "VI_DATA10")
MUXCTRL(DV300_iocfg_reg27, 0x114F0024, "MIPI_RX_D3P", "VI_DATA11")
MUXCTRL(DV300_iocfg_reg28, 0x114F0028, "MIPI_RX_CK0N", "VI_DATA13")
MUXCTRL(DV300_iocfg_reg29, 0x114F002C, "MIPI_RX_CK0P", "VI_DATA12")
MUXCTRL(DV300_iocfg_reg30, 0x114F0030, "MIPI_RX_D0N")
MUXCTRL(DV300_iocfg_reg31, 0x114F0034, "MIPI_RX_D0P")
MUXCTRL(DV300_iocfg_reg32, 0x114F0038, "MIPI_RX_D1N")
MUXCTRL(DV300_iocfg_reg33, 0x114F003C, "MIPI_RX_D1P")
MUXCTRL(DV300_iocfg_reg34, 0x114F0040, "GPIO3_0", "VI_DATA0", "VOU656_DATA0",
        "I2C5_SCL")
MUXCTRL(DV300_iocfg_reg35, 0x114F0044, "GPIO3_1", "VI_DATA1", "VOU656_DATA1",
        "I2C5_SDA")
MUXCTRL(DV300_iocfg_reg36, 0x114F0048, "GPIO3_2", "VI_DATA2", "VOU656_DATA2",
        "I2C6_SCL")
MUXCTRL(DV300_iocfg_reg37, 0x114F004C, "GPIO3_3", "VI_DATA3", "VOU656_DATA3",
        "I2C6_SDA")
MUXCTRL(DV300_iocfg_reg38, 0x114F0050, "GPIO3_4", "VI_DATA4", "VOU656_DATA4",
        "UART2_RTSN", "SPI2_SCLK")
MUXCTRL(DV300_iocfg_reg39, 0x114F0054, "GPIO3_5", "VI_DATA5", "VOU656_DATA5",
        "UART2_CTSN", "SPI2_SDO")
MUXCTRL(DV300_iocfg_reg40, 0x114F0058, "GPIO3_6", "VI_DATA6", "VOU656_DATA6",
        "UART2_RXD", "SPI2_SDI")
MUXCTRL(DV300_iocfg_reg41, 0x114F005C, "GPIO3_7", "VI_DATA7", "VOU656_DATA7",
        "UART2_TXD", "SPI2_CSN")
MUXCTRL(DV300_iocfg_reg42, 0x114F0060, "GPIO4_6", "VI_VS", "SENSOR1_CLK",
        "FLASH_TRIG", "SENSOR_VS")
MUXCTRL(DV300_iocfg_reg43, 0x114F0064, "GPIO4_7", "VI_HS", "SENSOR1_RSTN",
        "SHUTTER_TRIG", "SENSOR_HS")
MUXCTRL(DV300_iocfg_reg44, 0x114F0068, "GPIO2_3", "VI_CLK", "VOU656_CLK")
MUXCTRL(DV300_iocfg_reg45, 0x114F006C, "GPIO4_0", "SENSOR0_CLK")
MUXCTRL(DV300_iocfg_reg46, 0x114F0070, "GPIO4_1", "SENSOR0_RSTN", "BOOT_SEL1")
MUXCTRL(DV300_iocfg_reg47, 0x114F0074, "GPIO4_2", "SPI0_SCLK", "I2C0_SCL",
        "SPI_3LINE_SCLK")
MUXCTRL(DV300_iocfg_reg48, 0x114F0078, "GPIO4_3", "SPI0_SDO", "I2C0_SDA",
        "SPI_3LINE_SDATA")
MUXCTRL(DV300_iocfg_reg49, 0x114F007C, "GPIO4_4", "SPI0_SDI", "I2C1_SDA",
        "reserved", "SENSOR_VS")
MUXCTRL(DV300_iocfg_reg50, 0x114F0080, "GPIO4_5", "SPI0_CSN", "I2C1_SCL",
        "SPI_3LINE_CSN", "SENSOR_HS")
MUXCTRL(DV300_iocfg_reg51, 0x111F0000, "GPIO5_0", "UART1_RTSN", "UART4_RXD")
MUXCTRL(DV300_iocfg_reg52, 0x111F0004, "GPIO5_1", "UART1_CTSN", "UART4_TXD")
MUXCTRL(DV300_iocfg_reg53, 0x111F0008, "GPIO5_2", "UART1_RXD")
MUXCTRL(DV300_iocfg_reg54, 0x111F000C, "GPIO5_3", "UART1_TXD")
MUXCTRL(DV300_iocfg_reg55, 0x111F0010, "GPIO5_4", "UART0_RXD")
MUXCTRL(DV300_iocfg_reg56, 0x111F0014, "GPIO5_5", "UART0_TXD")
MUXCTRL(DV300_iocfg_reg57, 0x111F0018, "GPIO5_6", "I2C2_SDA")
MUXCTRL(DV300_iocfg_reg58, 0x111F001C, "GPIO5_7", "I2C2_SCL")
MUXCTRL(DV300_iocfg_reg59, 0x111F0020, "TEST_MODE")
MUXCTRL(DV300_iocfg_reg60, 0x111F0024, "GPIO6_6", "PWM0")
MUXCTRL(DV300_iocfg_reg61, 0x111F0028, "GPIO6_7", "PWM1")
MUXCTRL(DV300_iocfg_reg62, 0x111F002C, "SVB_PWM", "GPIO10_2")
MUXCTRL(DV300_iocfg_reg63, 0x111F0030, "LSADC_CH0", "GPIO10_3")
MUXCTRL(DV300_iocfg_reg64, 0x111F0034, "LSADC_CH1", "GPIO10_4")
MUXCTRL(DV300_iocfg_reg65, 0x112F0000, "GPIO10_6", "I2C7_SCL")
MUXCTRL(DV300_iocfg_reg66, 0x112F0004, "GPIO10_7", "I2C7_SDA", "RMII_CLK")
MUXCTRL(DV300_iocfg_reg67, 0x112F0008, "GPIO6_0", "SDIO1_CCLK_OUT",
        "RMII_RX_DV")
MUXCTRL(DV300_iocfg_reg68, 0x112F000C, "GPIO6_1", "SDIO1_CCMD", "EPHY_CLK")
MUXCTRL(DV300_iocfg_reg69, 0x112F0010, "GPIO6_2", "SDIO1_CDATA0", "MDCK")
MUXCTRL(DV300_iocfg_reg70, 0x112F0014, "GPIO6_3", "SDIO1_CDATA1", "MDIO")
MUXCTRL(DV300_iocfg_reg71, 0x112F0018, "GPIO6_4", "SDIO1_CDATA2", "RMII_TX_EN")
MUXCTRL(DV300_iocfg_reg72, 0x112F001C, "GPIO6_5", "SDIO1_CDATA3", "EPHY_RSTN")
MUXCTRL(DV300_iocfg_reg73, 0x112F0020, "JTAG_TRSTN", "SPI1_SCLK", "RMII_TXD1",
        "I2S_MCLK", "GPIO8_0")
MUXCTRL(DV300_iocfg_reg74, 0x112F0024, "JTAG_TCK", "SPI1_SDO", "RMII_RXD1",
        "I2S_BCLK_TX", "GPIO8_1")
MUXCTRL(DV300_iocfg_reg75, 0x112F0028, "JTAG_TMS", "SPI1_CSN0", "RMII_TXD0",
        "I2S_WS_TX", "GPIO8_2")
MUXCTRL(DV300_iocfg_reg76, 0x112F002C, "JTAG_TDO", "SPI1_SDI", "RMII_RXD0",
        "I2S_SD_TX", "GPIO8_3")
MUXCTRL(DV300_iocfg_reg77, 0x112F0030, "JTAG_TDI", "SPI1_CSN1", "LCD_DATA23",
        "I2S_SD_RX", "GPIO8_4")
MUXCTRL(DV300_iocfg_reg78, 0x112F0034, "GPIO0_6", "reserved", "LCD_CLK",
        "VOU1120_CLK/VOU656_CLK")
MUXCTRL(DV300_iocfg_reg79, 0x112F0038, "GPIO8_5", "MDIO", "LCD_DATA5",
        "VOU1120_DATA2/VOU656_DATA2")
MUXCTRL(DV300_iocfg_reg80, 0x112F003C, "GPIO8_6", "MDCK", "LCD_DATA4",
        "VOU1120_DATA3/VOU656_DATA3", "BOOT_SEL0")
MUXCTRL(DV300_iocfg_reg81, 0x112F0040, "TEST_CLK", "RMII_TXD1", "LCD_DATA1",
        "VOU1120_DATA6/VOU656_DATA6", "GPIO8_7")
MUXCTRL(DV300_iocfg_reg82, 0x112F0044, "GPIO7_0", "RMII_TX_EN", "LCD_DATA2",
        "VOU1120_DATA5/VOU656_DATA5")
MUXCTRL(DV300_iocfg_reg83, 0x112F0048, "GPIO7_1", "RMII_TXD0", "LCD_DATA0",
        "VOU1120_DATA7/VOU656_DATA7")
MUXCTRL(DV300_iocfg_reg84, 0x112F004C, "GPIO7_2", "RMII_CLK", "LCD_HSYNC")
MUXCTRL(DV300_iocfg_reg85, 0x112F0050, "GPIO7_3", "RMII_RX_DV", "LCD_DATA6",
        "VOU1120_DATA1/VOU656_DATA1")
MUXCTRL(DV300_iocfg_reg86, 0x112F0054, "GPIO7_4", "RMII_RXD1", "LCD_VSYNC")
MUXCTRL(DV300_iocfg_reg87, 0x112F0058, "GPIO7_5", "RMII_RXD0", "LCD_DE")
MUXCTRL(DV300_iocfg_reg88, 0x112F005C, "GPIO7_6", "EPHY_RSTN", "LCD_DATA3",
        "VOU1120_DATA4/VOU656_DATA4", "SFC_DEVICE_MODE")
MUXCTRL(DV300_iocfg_reg89, 0x112F0060, "GPIO7_7", "EPHY_CLK", "LCD_DATA7",
        "VOU1120_DATA0/VOU656_DATA0")
MUXCTRL(DV300_iocfg_reg90, 0x112F0064, "DSI_D3P", "GPIO9_0", "LCD_DATA16",
        "SHUTTER_TRIG", "LCD_DATA5")
MUXCTRL(DV300_iocfg_reg91, 0x112F0068, "DSI_D3N", "GPIO9_1", "LCD_DATA17",
        "FLASH_TRIG", "LCD_CLK")
MUXCTRL(DV300_iocfg_reg92, 0x112F006C, "DSI_D2N", "GPIO9_2", "LCD_DATA14",
        "VOU1120_DATA9", "LCD_DATA3")
MUXCTRL(DV300_iocfg_reg93, 0x112F0070, "DSI_D2P", "GPIO9_3", "LCD_DATA15",
        "VOU1120_DATA8", "LCD_DATA4")
MUXCTRL(DV300_iocfg_reg94, 0x112F0074, "DSI_CKP", "GPIO9_4", "LCD_DATA12",
        "VOU1120_DATA11", "LCD_DATA1")
MUXCTRL(DV300_iocfg_reg95, 0x112F0078, "DSI_CKN", "GPIO9_5", "LCD_DATA13",
        "VOU1120_DATA10", "LCD_DATA2")
MUXCTRL(DV300_iocfg_reg96, 0x112F007C, "DSI_D1N", "GPIO9_6", "LCD_DATA10",
        "VOU1120_DATA13", "LCD_HSYNC")
MUXCTRL(DV300_iocfg_reg97, 0x112F0080, "DSI_D1P", "GPIO9_7", "LCD_DATA11",
        "VOU1120_DATA12", "LCD_DATA0")
MUXCTRL(DV300_iocfg_reg98, 0x112F0084, "DSI_D0P", "GPIO10_0", "LCD_DATA8",
        "VOU1120_DATA15", "LCD_DE")
MUXCTRL(DV300_iocfg_reg99, 0x112F0088, "DSI_D0N", "GPIO10_1", "LCD_DATA9",
        "VOU1120_DATA14", "LCD_VSYNC")
MUXCTRL(DV300_iocfg_reg100, 0x112F008C, "GPIO0_1", "I2C3_SDA", "LCD_DATA20")
MUXCTRL(DV300_iocfg_reg101, 0x112F0090, "GPIO0_2", "I2C3_SCL", "LCD_DATA19")
MUXCTRL(DV300_iocfg_reg102, 0x112F0094, "GPIO0_3", "IR_IN", "LCD_DATA18")
MUXCTRL(DV300_iocfg_reg103, 0x112F0098, "GPIO0_4", "reserved", "LCD_DATA21")
MUXCTRL(DV300_iocfg_reg104, 0x112F009C, "GPIO0_5", "reserved", "LCD_DATA22")
MUXCTRL(DV300_iocfg_reg105, 0x112F00A0, "GPIO0_0", "UPDATE_MODE")
MUXCTRL(DV300_iocfg_reg106, 0x112F00A4, "PWR_RSTN")
MUXCTRL(DV300_iocfg_reg107, 0x112F00A8, "PWR_WAKEUP", "GPIO11_0")
MUXCTRL(DV300_iocfg_reg108, 0x112F00AC, "PWR_SEQ0", "GPIO11_1")
MUXCTRL(DV300_iocfg_reg109, 0x112F00B0, "PWR_SEQ1", "GPIO11_2")
MUXCTRL(DV300_iocfg_reg110, 0x112F00B4, "PWR_STARTUP")
MUXCTRL(DV300_iocfg_reg111, 0x112F00B8, "PWR_EN", "GPIO11_3")
MUXCTRL(DV300_iocfg_reg112, 0x112F00BC, "PWR_BUTTON")

static const muxctrl_reg_t *DV300regs[] = {
    &DV300_iocfg_reg0,   &DV300_iocfg_reg1,   &DV300_iocfg_reg2,
    &DV300_iocfg_reg3,   &DV300_iocfg_reg4,   &DV300_iocfg_reg5,
    &DV300_iocfg_reg6,   &DV300_iocfg_reg7,   &DV300_iocfg_reg8,
    &DV300_iocfg_reg9,   &DV300_iocfg_reg10,  &DV300_iocfg_reg11,
    &DV300_iocfg_reg12,  &DV300_iocfg_reg13,  &DV300_iocfg_reg14,
    &DV300_iocfg_reg15,  &DV300_iocfg_reg16,  &DV300_iocfg_reg17,
    &DV300_iocfg_reg18,  &DV300_iocfg_reg19,  &DV300_iocfg_reg20,
    &DV300_iocfg_reg21,  &DV300_iocfg_reg22,  &DV300_iocfg_reg23,
    &DV300_iocfg_reg24,  &DV300_iocfg_reg25,  &DV300_iocfg_reg26,
    &DV300_iocfg_reg27,  &DV300_iocfg_reg28,  &DV300_iocfg_reg29,
    &DV300_iocfg_reg30,  &DV300_iocfg_reg31,  &DV300_iocfg_reg32,
    &DV300_iocfg_reg33,  &DV300_iocfg_reg34,  &DV300_iocfg_reg35,
    &DV300_iocfg_reg36,  &DV300_iocfg_reg37,  &DV300_iocfg_reg38,
    &DV300_iocfg_reg39,  &DV300_iocfg_reg40,  &DV300_iocfg_reg41,
    &DV300_iocfg_reg42,  &DV300_iocfg_reg43,  &DV300_iocfg_reg44,
    &DV300_iocfg_reg45,  &DV300_iocfg_reg46,  &DV300_iocfg_reg47,
    &DV300_iocfg_reg48,  &DV300_iocfg_reg49,  &DV300_iocfg_reg50,
    &DV300_iocfg_reg51,  &DV300_iocfg_reg52,  &DV300_iocfg_reg53,
    &DV300_iocfg_reg54,  &DV300_iocfg_reg55,  &DV300_iocfg_reg56,
    &DV300_iocfg_reg57,  &DV300_iocfg_reg58,  &DV300_iocfg_reg59,
    &DV300_iocfg_reg60,  &DV300_iocfg_reg61,  &DV300_iocfg_reg62,
    &DV300_iocfg_reg63,  &DV300_iocfg_reg64,  &DV300_iocfg_reg65,
    &DV300_iocfg_reg66,  &DV300_iocfg_reg67,  &DV300_iocfg_reg68,
    &DV300_iocfg_reg69,  &DV300_iocfg_reg70,  &DV300_iocfg_reg71,
    &DV300_iocfg_reg72,  &DV300_iocfg_reg73,  &DV300_iocfg_reg74,
    &DV300_iocfg_reg75,  &DV300_iocfg_reg76,  &DV300_iocfg_reg77,
    &DV300_iocfg_reg78,  &DV300_iocfg_reg79,  &DV300_iocfg_reg80,
    &DV300_iocfg_reg81,  &DV300_iocfg_reg82,  &DV300_iocfg_reg83,
    &DV300_iocfg_reg84,  &DV300_iocfg_reg85,  &DV300_iocfg_reg86,
    &DV300_iocfg_reg87,  &DV300_iocfg_reg88,  &DV300_iocfg_reg89,
    &DV300_iocfg_reg90,  &DV300_iocfg_reg91,  &DV300_iocfg_reg92,
    &DV300_iocfg_reg93,  &DV300_iocfg_reg94,  &DV300_iocfg_reg95,
    &DV300_iocfg_reg96,  &DV300_iocfg_reg97,  &DV300_iocfg_reg98,
    &DV300_iocfg_reg99,  &DV300_iocfg_reg100, &DV300_iocfg_reg101,
    &DV300_iocfg_reg102, &DV300_iocfg_reg103, &DV300_iocfg_reg104,
    &DV300_iocfg_reg105, &DV300_iocfg_reg106, &DV300_iocfg_reg107,
    &DV300_iocfg_reg108, &DV300_iocfg_reg109, &DV300_iocfg_reg110,
    &DV300_iocfg_reg111, &DV300_iocfg_reg112, 0,
};

MUXCTRL(EV200_iocfg_reg0, 0x100C0000, "GPIO0_1", "UART0_RXD")
MUXCTRL(EV200_iocfg_reg1, 0x100C0004, "GPIO0_2", "UART0_TXD")
MUXCTRL(EV200_iocfg_reg2, 0x100C0008, "GPIO0_0", "UPDATE_MODE")
MUXCTRL(EV200_iocfg_reg3, 0x100C000C, "GPIO0_3", "PWM0", "UART1_TXD",
        "I2C1_SCL")
MUXCTRL(EV200_iocfg_reg4, 0x100C0010, "GPIO0_4", "PWM1", "UART1_RXD",
        "I2C1_SDA")
MUXCTRL(EV200_iocfg_reg5, 0x100C0014, "EMMC_CLK", "SFC_CLK", "SFC_DEVICE_MODE")
MUXCTRL(EV200_iocfg_reg6, 0x100C0018, "EMMC_CMD", "SFC_MOSI_IO0")
MUXCTRL(EV200_iocfg_reg7, 0x100C001C, "EMMC_DATA0", "SFC_MISO_IO1")
MUXCTRL(EV200_iocfg_reg8, 0x100C0020, "EMMC_DATA3", "SFC_WP_IO2")
MUXCTRL(EV200_iocfg_reg9, 0x100C0024, "EMMC_DATA2", "SFC_HOLD_IO3")
MUXCTRL(EV200_iocfg_reg10, 0x100C0028, "EMMC_DATA1", "SFC_CSN")
MUXCTRL(EV200_iocfg_reg11, 0x100C002C, "SYS_RSTN_OUT")
MUXCTRL(EV200_iocfg_reg12, 0x100C0040, "GPIO4_0", "SDIO0_CCLK_OUT", "JTAG_TCK",
        "EMMC_CLK", "SDIO1_CCLK_OUT", "reserved", "VO_BT1120_DATA10",
        "SFC_INPUT_SEL")
MUXCTRL(EV200_iocfg_reg13, 0x100C0044, "GPIO4_1", "SDIO0_CCMD", "reserved",
        "EMMC_CMD", "SDIO1_CCMD", "reserved", "VO_BT1120_DATA11")
MUXCTRL(EV200_iocfg_reg14, 0x100C0048, "GPIO4_2", "SDIO0_CDATA0", "JTAG_TMS",
        "EMMC_DATA1", "SDIO1_CDATA3", "reserved", "VO_BT1120_DATA12")
MUXCTRL(EV200_iocfg_reg15, 0x100C004C, "GPIO4_3", "SDIO0_CDATA1", "JTAG_TDO",
        "EMMC_DATA2", "SDIO1_CDATA2", "reserved", "VO_BT1120_DATA13")
MUXCTRL(EV200_iocfg_reg16, 0x100C0050, "GPIO4_4", "SDIO0_CDATA2", "JTAG_TDI",
        "EMMC_DATA3", "SDIO1_CDATA1", "reserved", "VO_BT1120_DATA14")
MUXCTRL(EV200_iocfg_reg17, 0x100C0054, "GPIO4_5", "SDIO0_CDATA3", "JTAG_TRSTN",
        "EMMC_DATA0", "SDIO1_CDATA0", "reserved", "VO_BT1120_DATA15")
MUXCTRL(EV200_iocfg_reg18, 0x100C005C, "GPIO4_7", "SDIO0_CARD_DETECT",
        "reserved", "EMMC_RST_N")
MUXCTRL(EV200_iocfg_reg19, 0x112C0000, "MIPI_RX_CK0N", "reserved", "VI_CLK")
MUXCTRL(EV200_iocfg_reg20, 0x112C0004, "MIPI_RX_CK0P", "reserved", "VI_DATA7")
MUXCTRL(EV200_iocfg_reg21, 0x112C0008, "MIPI_RX_D0N", "reserved", "VI_DATA8")
MUXCTRL(EV200_iocfg_reg22, 0x112C000C, "MIPI_RX_D0P", "reserved", "VI_DATA9")
MUXCTRL(EV200_iocfg_reg23, 0x112C0010, "MIPI_RX_D2N", "reserved", "VI_DATA11")
MUXCTRL(EV200_iocfg_reg24, 0x112C0014, "MIPI_RX_D2P", "reserved", "VI_DATA10")
MUXCTRL(EV200_iocfg_reg25, 0x112C0028, "TEST_CLK", "SENSOR_CLK", "VI_DATA6",
        "reserved", "GPIO5_4")
MUXCTRL(EV200_iocfg_reg26, 0x112C002C, "GPIO5_5", "SENSOR_RSTN", "VI_DATA4")
MUXCTRL(EV200_iocfg_reg27, 0x112C0030, "GPIO5_6", "I2C0_SDA", "VI_DATA3")
MUXCTRL(EV200_iocfg_reg28, 0x112C0034, "GPIO5_7", "I2C0_SCL", "VI_DATA5")
MUXCTRL(EV200_iocfg_reg29, 0x112C0038, "GPIO6_2", "I2C2_SDA", "VI_DATA2",
        "reserved", "reserved", "reserved", "reserved", "SPI0_SDO")
MUXCTRL(EV200_iocfg_reg30, 0x112C003C, "GPIO6_3", "I2C2_SCL", "VI_DATA1",
        "reserved", "reserved", "reserved", "reserved", "SPI0_SCLK")
MUXCTRL(EV200_iocfg_reg31, 0x112C0040, "GPIO5_0", "ETH_LINK_STA_LED",
        "VI_DATA0", "reserved", "reserved", "reserved", "reserved", "SPI0_CSN")
MUXCTRL(EV200_iocfg_reg32, 0x112C0044, "GPIO5_1", "ETH_LINK_ACT_LED",
        "TEST_MODE")
MUXCTRL(EV200_iocfg_reg33, 0x112C0048, "GPIO8_7", "BOOT_SEL1", "SENSOR_RSTN",
        "VO_BT656_CLK", "SDIO1_CCLK_OUT", "LCD_CLK", "VO_BT1120_CLK",
        "SPI1_SCLK")
MUXCTRL(EV200_iocfg_reg34, 0x112C004C, "GPIO8_5", "reserved", "VI_HS",
        "VO_BT656_DATA0", "SDIO1_CCMD", "LCD_HS", "VO_BT1120_DATA8", "SPI1_SDI")
MUXCTRL(EV200_iocfg_reg35, 0x112C0050, "GPIO8_6", "reserved", "VI_VS",
        "VO_BT656_DATA1", "reserved", "LCD_VS", "VO_BT1120_DATA9", "SPI1_SDO")
MUXCTRL(EV200_iocfg_reg36, 0x112C0054, "GPIO8_4", "BOOT_SEL0", "SENSOR_CLK",
        "PWM2", "reserved", "LCD_DE", "reserved", "SPI1_CSN0")
MUXCTRL(EV200_iocfg_reg37, 0x112C0058, "GPIO7_0", "reserved", "I2C2_SCL",
        "VO_BT656_DATA4", "SDIO1_CDATA3", "LCD_DATA4", "VO_BT1120_DATA4",
        "SPI1_CSN1")
MUXCTRL(EV200_iocfg_reg38, 0x112C005C, "GPIO7_1", "reserved", "I2C2_SDA",
        "VO_BT656_DATA5", "SDIO1_CDATA2", "LCD_DATA5", "VO_BT1120_DATA5")
MUXCTRL(EV200_iocfg_reg39, 0x112C0060, "GPIO7_2", "reserved", "I2C0_SDA",
        "VO_BT656_DATA6", "SDIO1_CDATA1", "LCD_DATA6", "VO_BT1120_DATA6")
MUXCTRL(EV200_iocfg_reg40, 0x112C0064, "GPIO7_3", "reserved", "I2C0_SCL",
        "VO_BT656_DATA7", "SDIO1_CDATA0", "LCD_DATA7", "VO_BT1120_DATA7")
MUXCTRL(EV200_iocfg_reg41, 0x112C0068, "GPIO6_7", "reserved", "reserved",
        "VO_BT656_DATA3", "reserved", "LCD_DATA3", "VO_BT1120_DATA3",
        "SPI0_CSN")
MUXCTRL(EV200_iocfg_reg42, 0x112C006C, "GPIO6_6", "SFC_BOOT_MODE", "PWM3",
        "VO_BT656_DATA2", "reserved", "LCD_DATA2", "VO_BT1120_DATA2",
        "SPI0_SDO")
MUXCTRL(EV200_iocfg_reg43, 0x112C0070, "GPIO6_5", "reserved", "UART1_RXD",
        "reserved", "reserved", "LCD_DATA1", "VO_BT1120_DATA1", "SPI0_SDI")
MUXCTRL(EV200_iocfg_reg44, 0x112C0074, "GPIO6_4", "reserved", "UART1_TXD",
        "reserved", "reserved", "LCD_DATA0", "VO_BT1120_DATA0", "SPI0_SCLK")
MUXCTRL(EV200_iocfg_reg45, 0x120C0000, "GPIO1_0", "LSADC_CH0")
MUXCTRL(EV200_iocfg_reg46, 0x120C0004, "GPIO1_1", "LSADC_CH1")
MUXCTRL(EV200_iocfg_reg47, 0x120C0010, "JTAG_TRSTN", "SPI1_CSN0", "GPIO1_4",
        "reserved", "UART2_RXD", "I2S_MCLK")
MUXCTRL(EV200_iocfg_reg48, 0x120C0014, "JTAG_TCK", "SPI1_SCLK", "GPIO1_5",
        "reserved", "UART2_TXD", "I2S_BCLK")
MUXCTRL(EV200_iocfg_reg49, 0x120C0018, "JTAG_TMS", "SPI1_SDI", "GPIO1_6",
        "PWM2", "UART2_CTSN", "I2S_WS")
MUXCTRL(EV200_iocfg_reg50, 0x120C001C, "JTAG_TDO", "SPI1_SDO", "GPIO1_7",
        "reserved", "UART2_RTSN", "I2S_SD_RX")
MUXCTRL(EV200_iocfg_reg51, 0x120C0020, "JTAG_TDI", "SPI1_CSN1", "GPIO2_0",
        "SDIO0_CARD_POWER_EN", "PWM3", "I2S_SD_TX")

static const muxctrl_reg_t *EV200regs[] = {
    &EV200_iocfg_reg0,
    &EV200_iocfg_reg1,
    &EV200_iocfg_reg2,
    &EV200_iocfg_reg3,
    &EV200_iocfg_reg4,
    &EV200_iocfg_reg5,
    &EV200_iocfg_reg6,
    &EV200_iocfg_reg7,
    &EV200_iocfg_reg8,
    &EV200_iocfg_reg9,
    &EV200_iocfg_reg10,
    &EV200_iocfg_reg11,
    &EV200_iocfg_reg12,
    &EV200_iocfg_reg13,
    &EV200_iocfg_reg14,
    &EV200_iocfg_reg15,
    &EV200_iocfg_reg16,
    &EV200_iocfg_reg17,
    &EV200_iocfg_reg18,
    &EV200_iocfg_reg19,
    &EV200_iocfg_reg20,
    &EV200_iocfg_reg21,
    &EV200_iocfg_reg22,
    &EV200_iocfg_reg23,
    &EV200_iocfg_reg24,
    &EV200_iocfg_reg25,
    &EV200_iocfg_reg26,
    &EV200_iocfg_reg27,
    &EV200_iocfg_reg28,
    &EV200_iocfg_reg29,
    &EV200_iocfg_reg30,
    &EV200_iocfg_reg31,
    &EV200_iocfg_reg32,
    &EV200_iocfg_reg33,
    &EV200_iocfg_reg34,
    &EV200_iocfg_reg35,
    &EV200_iocfg_reg36,
    &EV200_iocfg_reg37,
    &EV200_iocfg_reg38,
    &EV200_iocfg_reg39,
    &EV200_iocfg_reg40,
    &EV200_iocfg_reg41,
    &EV200_iocfg_reg42,
    &EV200_iocfg_reg43,
    &EV200_iocfg_reg44,
    &EV200_iocfg_reg45,
    &EV200_iocfg_reg46,
    &EV200_iocfg_reg47,
    &EV200_iocfg_reg48,
    &EV200_iocfg_reg49,
    &EV200_iocfg_reg50,
    &EV200_iocfg_reg51,
    0,
};

MUXCTRL(EV300_iocfg_reg0, 0x100C0000, "GPIO0_1", "UART0_RXD")
MUXCTRL(EV300_iocfg_reg1, 0x100C0004, "GPIO0_2", "UART0_TXD")
MUXCTRL(EV300_iocfg_reg2, 0x100C0008, "GPIO0_0", "UPDATE_MODE")
MUXCTRL(EV300_iocfg_reg3, 0x100C000C, "GPIO0_3", "PWM0", "UART1_TXD",
        "I2C1_SCL")
MUXCTRL(EV300_iocfg_reg4, 0x100C0010, "GPIO0_4", "PWM1", "UART1_RXD",
        "I2C1_SDA")
MUXCTRL(EV300_iocfg_reg5, 0x100C0014, "EMMC_CLK", "SFC_CLK", "SFC_DEVICE_MODE")
MUXCTRL(EV300_iocfg_reg6, 0x100C0018, "EMMC_CMD", "SFC_MOSI_IO0")
MUXCTRL(EV300_iocfg_reg7, 0x100C001C, "EMMC_DATA0", "SFC_MISO_IO1")
MUXCTRL(EV300_iocfg_reg8, 0x100C0020, "EMMC_DATA3", "SFC_WP_IO2")
MUXCTRL(EV300_iocfg_reg9, 0x100C0024, "EMMC_DATA2", "SFC_HOLD_IO3")
MUXCTRL(EV300_iocfg_reg10, 0x100C0028, "EMMC_DATA1", "SFC_CSN")
MUXCTRL(EV300_iocfg_reg11, 0x100C002C, "SYS_RSTN_OUT", "WDG_RSTN")
MUXCTRL(EV300_iocfg_reg12, 0x100C0030, "GPIO3_4", "reserved", "reserved",
        "EMMC_DATA4")
MUXCTRL(EV300_iocfg_reg13, 0x100C0034, "GPIO3_5", "reserved", "reserved",
        "EMMC_DATA5")
MUXCTRL(EV300_iocfg_reg14, 0x100C0038, "GPIO3_6", "reserved", "reserved",
        "EMMC_DATA6")
MUXCTRL(EV300_iocfg_reg15, 0x100C003C, "GPIO3_7", "reserved", "reserved",
        "EMMC_DATA7")
MUXCTRL(EV300_iocfg_reg16, 0x100C0040, "GPIO4_0", "SDIO0_CCLK_OUT", "JTAG_TCK",
        "EMMC_CLK", "SDIO1_CCLK_OUT", "reserved", "reserved", "SFC_INPUT_SEL")
MUXCTRL(EV300_iocfg_reg17, 0x100C0044, "GPIO4_1", "SDIO0_CCMD", "reserved",
        "EMMC_CMD", "SDIO1_CCMD")
MUXCTRL(EV300_iocfg_reg18, 0x100C0048, "GPIO4_2", "SDIO0_CDATA0", "JTAG_TMS",
        "EMMC_DATA1", "SDIO1_CDATA3")
MUXCTRL(EV300_iocfg_reg19, 0x100C004C, "GPIO4_3", "SDIO0_CDATA1", "JTAG_TDO",
        "EMMC_DATA2", "SDIO1_CDATA2")
MUXCTRL(EV300_iocfg_reg20, 0x100C0050, "GPIO4_4", "SDIO0_CDATA2", "JTAG_TDI",
        "EMMC_DATA3", "SDIO1_CDATA1")
MUXCTRL(EV300_iocfg_reg21, 0x100C0054, "GPIO4_5", "SDIO0_CDATA3", "JTAG_TRSTN",
        "EMMC_DATA0", "SDIO1_CDATA0")
MUXCTRL(EV300_iocfg_reg22, 0x100C0058, "GPIO4_6", "SDIO0_CARD_POWER_EN_N",
        "reserved", "EMMC_DS")
MUXCTRL(EV300_iocfg_reg23, 0x100C005C, "GPIO4_7", "SDIO0_CARD_DETECT",
        "reserved", "EMMC_RST_N")
MUXCTRL(EV300_iocfg_reg24, 0x100C0060, "GPIO2_1", "SFC_CLK", "reserved",
        "reserved", "SDIO1_CCLK_OUT")
MUXCTRL(EV300_iocfg_reg25, 0x100C0064, "GPIO2_2", "SFC_WP_IO2", "reserved",
        "reserved", "SDIO1_CCMD")
MUXCTRL(EV300_iocfg_reg26, 0x100C0068, "GPIO3_0", "SFC_MOSI_IO0", "reserved",
        "reserved", "SDIO1_CDATA0")
MUXCTRL(EV300_iocfg_reg27, 0x100C006C, "GPIO3_1", "SFC_HOLD_IO3", "reserved",
        "reserved", "SDIO1_CDATA1")
MUXCTRL(EV300_iocfg_reg28, 0x100C0070, "GPIO3_2", "SFC_CSN", "reserved",
        "reserved", "SDIO1_CDATA2")
MUXCTRL(EV300_iocfg_reg29, 0x100C0074, "GPIO3_3", "SFC_MISO_IO1", "reserved",
        "reserved", "SDIO1_CDATA3")
MUXCTRL(EV300_iocfg_reg30, 0x100C0078, "GPIO0_5", "USB_OVRCUR")
MUXCTRL(EV300_iocfg_reg31, 0x100C007C, "GPIO0_6", "USB_VBUS")
MUXCTRL(EV300_iocfg_reg32, 0x100C0080, "GPIO0_7", "USB_PWREN")
MUXCTRL(EV300_iocfg_reg33, 0x100C0084, "GPIO2_4", "SPI1_SCLK")
MUXCTRL(EV300_iocfg_reg34, 0x100C0088, "GPIO2_5", "SPI1_SDO")
MUXCTRL(EV300_iocfg_reg35, 0x100C008C, "GPIO2_6", "SPI1_CSN0")
MUXCTRL(EV300_iocfg_reg36, 0x100C0090, "GPIO2_7", "SPI1_SDI")
MUXCTRL(EV300_iocfg_reg37, 0x100C0094, "RST_N")
MUXCTRL(EV300_iocfg_reg38, 0x100C0098, "POR_SEL")
MUXCTRL(EV300_iocfg_reg39, 0x100C009C, "GPIO9_0", "PWM2")
MUXCTRL(EV300_iocfg_reg40, 0x100C00A0, "GPIO9_1", "PWM3")
MUXCTRL(EV300_iocfg_reg41, 0x100C00A4, "GPIO2_3", "SVB_PWM")
MUXCTRL(EV300_iocfg_reg42, 0x112C0000, "MIPI_RX_CK0N", "VI_BT1120_DATA10",
        "VI_CLK")
MUXCTRL(EV300_iocfg_reg43, 0x112C0004, "MIPI_RX_CK0P", "VI_BT1120_DATA11",
        "VI_DATA7")
MUXCTRL(EV300_iocfg_reg44, 0x112C0008, "MIPI_RX_D0N", "VI_BT1120_DATA12",
        "reserved", "VI_DATA9")
MUXCTRL(EV300_iocfg_reg45, 0x112C000C, "MIPI_RX_D0P", "VI_BT1120_DATA13",
        "reserved", "VI_DATA8")
MUXCTRL(EV300_iocfg_reg46, 0x112C0010, "MIPI_RX_D2N", "VI_BT1120_DATA14",
        "reserved", "VI_DATA10")
MUXCTRL(EV300_iocfg_reg47, 0x112C0014, "MIPI_RX_D2P", "VI_BT1120_DATA15",
        "reserved", "VI_DATA11")
MUXCTRL(EV300_iocfg_reg48, 0x112C0018, "MIPI_RX_D1N", "VI_BT1120_DATA6",
        "reserved", "VI_DATA6")
MUXCTRL(EV300_iocfg_reg49, 0x112C001C, "MIPI_RX_D1P", "VI_BT1120_DATA7",
        "reserved", "VI_DATA4")
MUXCTRL(EV300_iocfg_reg50, 0x112C0020, "MIPI_RX_D3N", "VI_BT1120_DATA8",
        "reserved", "VI_DATA3")
MUXCTRL(EV300_iocfg_reg51, 0x112C0024, "MIPI_RX_D3P", "VI_BT1120_DATA9",
        "reserved", "VI_DATA5")
MUXCTRL(EV300_iocfg_reg52, 0x112C0028, "TEST_CLK", "SENSOR_CLK", "reserved",
        "reserved", "GPIO5_4")
MUXCTRL(EV300_iocfg_reg53, 0x112C002C, "GPIO5_5", "SENSOR_RSTN")
MUXCTRL(EV300_iocfg_reg54, 0x112C0030, "GPIO5_6", "I2C0_SDA")
MUXCTRL(EV300_iocfg_reg55, 0x112C0034, "GPIO5_7", "I2C0_SCL")
MUXCTRL(EV300_iocfg_reg56, 0x112C0038, "GPIO6_2", "I2C2_SDA", "reserved",
        "VI_HS", "reserved", "reserved", "reserved", "SPI0_SDO")
MUXCTRL(EV300_iocfg_reg57, 0x112C003C, "GPIO6_3", "I2C2_SCL", "reserved",
        "VI_VS", "reserved", "reserved", "reserved", "SPI0_SCLK")
MUXCTRL(EV300_iocfg_reg58, 0x112C0040, "GPIO5_0", "ETH_LINK_STA_LED",
        "reserved", "VI_DATA2", "reserved", "reserved", "reserved", "SPI0_CSN")
MUXCTRL(EV300_iocfg_reg59, 0x112C0044, "GPIO5_1", "ETH_LINK_ACT_LED",
        "TEST_MODE")
MUXCTRL(EV300_iocfg_reg60, 0x112C0048, "GPIO8_7", "BOOT_SEL1", "SENSOR_RSTN",
        "VO_BT656_CLK", "SDIO1_CCLK_OUT", "LCD_CLK", "VO_BT1120_CLK",
        "SPI1_SCLK")
MUXCTRL(EV300_iocfg_reg61, 0x112C004C, "GPIO8_5", "VI_BT1120_DATA0", "VI_HS",
        "VO_BT656_DATA0", "SDIO1_CCMD", "LCD_HS", "VO_BT1120_DATA8", "SPI1_SDI")
MUXCTRL(EV300_iocfg_reg62, 0x112C0050, "GPIO8_6", "VI_BT1120_DATA1", "VI_VS",
        "VO_BT656_DATA1", "reserved", "LCD_VS", "VO_BT1120_DATA9", "SPI1_SDO")
MUXCTRL(EV300_iocfg_reg63, 0x112C0054, "GPIO8_4", "BOOT_SEL0", "SENSOR_CLK",
        "PWM2", "reserved", "LCD_DE", "reserved", "SPI1_CSN0")
MUXCTRL(EV300_iocfg_reg64, 0x112C0058, "GPIO7_0", "VI_BT1120_DATA4", "I2C2_SCL",
        "VO_BT656_DATA4", "SDIO1_CDATA3", "LCD_DATA4", "VO_BT1120_DATA4",
        "SPI1_CSN1", "LCD_DATA3")
MUXCTRL(EV300_iocfg_reg65, 0x112C005C, "GPIO7_1", "VI_BT1120_DATA5", "I2C2_SDA",
        "VO_BT656_DATA5", "SDIO1_CDATA2", "LCD_DATA5", "VO_BT1120_DATA5",
        "VI_DATA0", "LCD_DATA2")
MUXCTRL(EV300_iocfg_reg66, 0x112C0060, "GPIO7_2", "VI_BT1120_CLK", "I2C0_SDA",
        "VO_BT656_DATA6", "SDIO1_CDATA1", "LCD_DATA6", "VO_BT1120_DATA6",
        "VI_DATA1", "LCD_DATA1")
MUXCTRL(EV300_iocfg_reg67, 0x112C0064, "GPIO7_3", "reserved", "I2C0_SCL",
        "VO_BT656_DATA7", "SDIO1_CDATA0", "LCD_DATA7", "VO_BT1120_DATA7",
        "VI_DATA2", "LCD_DATA0")
MUXCTRL(EV300_iocfg_reg68, 0x112C0068, "GPIO6_7", "VI_BT1120_DATA3", "reserved",
        "VO_BT656_DATA3", "LCD_DE", "LCD_DATA3", "VO_BT1120_DATA3", "SPI0_CSN",
        "LCD_DATA4")
MUXCTRL(EV300_iocfg_reg69, 0x112C006C, "GPIO6_6", "SFC_BOOT_MODE", "PWM3",
        "VO_BT656_DATA2", "LCD_VS", "LCD_DATA2", "VO_BT1120_DATA2", "SPI0_SDO",
        "LCD_DATA5")
MUXCTRL(EV300_iocfg_reg70, 0x112C0070, "GPIO6_5", "VI_BT1120_DATA2",
        "UART1_RXD", "reserved", "LCD_HS", "LCD_DATA1", "VO_BT1120_DATA1",
        "SPI0_SDI", "LCD_DATA6")
MUXCTRL(EV300_iocfg_reg71, 0x112C0074, "GPIO6_4", "reserved", "UART1_TXD",
        "reserved", "LCD_CLK", "LCD_DATA0", "VO_BT1120_DATA0", "SPI0_SCLK",
        "LCD_DATA7")
MUXCTRL(EV300_iocfg_reg72, 0x112C0078, "GPIO7_4", "UART1_TXD", "reserved",
        "reserved", "LCD_DATA0", "LCD_DATA8", "reserved", "reserved",
        "LCD_DATA15")
MUXCTRL(EV300_iocfg_reg73, 0x112C007C, "GPIO7_5", "UART1_RXD", "reserved",
        "reserved", "LCD_DATA1", "LCD_DATA9", "reserved", "reserved",
        "LCD_DATA14")
MUXCTRL(EV300_iocfg_reg74, 0x112C0080, "GPIO7_6", "UART1_CTSN", "reserved",
        "reserved", "LCD_DATA2", "LCD_DATA10", "VO_BT1120_DATA10", "reserved",
        "LCD_DATA13")
MUXCTRL(EV300_iocfg_reg75, 0x112C0084, "GPIO7_7", "UART1_RTSN", "reserved",
        "reserved", "LCD_DATA3", "LCD_DATA11", "VO_BT1120_DATA11", "reserved",
        "LCD_DATA12")
MUXCTRL(EV300_iocfg_reg76, 0x112C0088, "GPIO8_0", "reserved", "reserved",
        "reserved", "LCD_DATA4", "LCD_DATA12", "VO_BT1120_DATA12", "reserved",
        "LCD_DATA11")
MUXCTRL(EV300_iocfg_reg77, 0x112C008C, "GPIO8_1", "reserved", "reserved",
        "reserved", "LCD_DATA5", "LCD_DATA13", "VO_BT1120_DATA13", "reserved",
        "LCD_DATA10")
MUXCTRL(EV300_iocfg_reg78, 0x112C0090, "GPIO8_2", "reserved", "reserved",
        "reserved", "LCD_DATA6", "LCD_DATA14", "VO_BT1120_DATA14", "reserved",
        "LCD_DATA9")
MUXCTRL(EV300_iocfg_reg79, 0x112C0094, "GPIO8_3", "reserved", "reserved",
        "reserved", "LCD_DATA7", "LCD_DATA15", "VO_BT1120_DATA15", "reserved",
        "LCD_DATA8")
MUXCTRL(EV300_iocfg_reg80, 0x112C0098, "GPIO5_2", "FLASH_TRIG", "SENSOR_HS")
MUXCTRL(EV300_iocfg_reg81, 0x112C009C, "GPIO5_3", "SHUTTER_TRIG", "SENSOR_VS",
        "reserved", "SPI0_CSN")
MUXCTRL(EV300_iocfg_reg82, 0x112C00A0, "GPIO6_0", "I2C1_SDA", "reserved",
        "reserved", "SPI0_SDO")
MUXCTRL(EV300_iocfg_reg83, 0x112C00A4, "GPIO6_1", "I2C1_SCL", "reserved",
        "reserved", "SPI0_SCLK")
MUXCTRL(EV300_iocfg_reg84, 0x120C0000, "GPIO1_0", "LSADC_CH0")
MUXCTRL(EV300_iocfg_reg85, 0x120C0004, "GPIO1_1", "LSADC_CH1")
MUXCTRL(EV300_iocfg_reg86, 0x120C0008, "GPIO1_2", "LSADC_CH2")
MUXCTRL(EV300_iocfg_reg87, 0x120C000C, "GPIO1_3", "LSADC_CH3")
MUXCTRL(EV300_iocfg_reg88, 0x120C0010, "JTAG_TRSTN", "SPI1_CSN0", "GPIO1_4",
        "reserved", "UART2_RXD", "I2S_MCLK")
MUXCTRL(EV300_iocfg_reg89, 0x120C0014, "JTAG_TCK", "SPI1_SCLK", "GPIO1_5",
        "reserved", "UART2_TXD", "I2S_BCLK")
MUXCTRL(EV300_iocfg_reg90, 0x120C0018, "JTAG_TMS", "SPI1_SDI", "GPIO1_6",
        "PWM2", "UART2_CTSN", "I2S_WS")
MUXCTRL(EV300_iocfg_reg91, 0x120C001C, "JTAG_TDO", "SPI1_SDO", "GPIO1_7",
        "reserved", "UART2_RTSN", "I2S_SD_RX")
MUXCTRL(EV300_iocfg_reg92, 0x120C0020, "JTAG_TDI", "SPI1_CSN1", "GPIO2_0",
        "SDIO0_CARD_POWER_EN_N", "PWM3", "I2S_SD_TX")

static const muxctrl_reg_t *EV300regs[] = {
    &EV300_iocfg_reg0,  &EV300_iocfg_reg1,
    &EV300_iocfg_reg2,  &EV300_iocfg_reg3,
    &EV300_iocfg_reg4,  &EV300_iocfg_reg5,
    &EV300_iocfg_reg6,  &EV300_iocfg_reg7,
    &EV300_iocfg_reg8,  &EV300_iocfg_reg9,
    &EV300_iocfg_reg10, &EV300_iocfg_reg11,
    &EV300_iocfg_reg12, &EV300_iocfg_reg13,
    &EV300_iocfg_reg14, &EV300_iocfg_reg15,
    &EV300_iocfg_reg16, &EV300_iocfg_reg17,
    &EV300_iocfg_reg18, &EV300_iocfg_reg19,
    &EV300_iocfg_reg20, &EV300_iocfg_reg21,
    &EV300_iocfg_reg22, &EV300_iocfg_reg23,
    &EV300_iocfg_reg24, &EV300_iocfg_reg25,
    &EV300_iocfg_reg26, &EV300_iocfg_reg27,
    &EV300_iocfg_reg28, &EV300_iocfg_reg29,
    &EV300_iocfg_reg30, &EV300_iocfg_reg31,
    &EV300_iocfg_reg32, &EV300_iocfg_reg33,
    &EV300_iocfg_reg34, &EV300_iocfg_reg35,
    &EV300_iocfg_reg36, &EV300_iocfg_reg37,
    &EV300_iocfg_reg38, &EV300_iocfg_reg39,
    &EV300_iocfg_reg40, &EV300_iocfg_reg41,
    &EV300_iocfg_reg42, &EV300_iocfg_reg43,
    &EV300_iocfg_reg44, &EV300_iocfg_reg45,
    &EV300_iocfg_reg46, &EV300_iocfg_reg47,
    &EV300_iocfg_reg48, &EV300_iocfg_reg49,
    &EV300_iocfg_reg50, &EV300_iocfg_reg51,
    &EV300_iocfg_reg52, &EV300_iocfg_reg53,
    &EV300_iocfg_reg54, &EV300_iocfg_reg55,
    &EV300_iocfg_reg56, &EV300_iocfg_reg57,
    &EV300_iocfg_reg58, &EV300_iocfg_reg59,
    &EV300_iocfg_reg60, &EV300_iocfg_reg61,
    &EV300_iocfg_reg62, &EV300_iocfg_reg63,
    &EV300_iocfg_reg64, &EV300_iocfg_reg65,
    &EV300_iocfg_reg66, &EV300_iocfg_reg67,
    &EV300_iocfg_reg68, &EV300_iocfg_reg69,
    &EV300_iocfg_reg70, &EV300_iocfg_reg71,
    &EV300_iocfg_reg72, &EV300_iocfg_reg73,
    &EV300_iocfg_reg74, &EV300_iocfg_reg75,
    &EV300_iocfg_reg76, &EV300_iocfg_reg77,
    &EV300_iocfg_reg78, &EV300_iocfg_reg79,
    &EV300_iocfg_reg80, &EV300_iocfg_reg81,
    &EV300_iocfg_reg82, &EV300_iocfg_reg83,
    &EV300_iocfg_reg84, &EV300_iocfg_reg85,
    &EV300_iocfg_reg86, &EV300_iocfg_reg87,
    &EV300_iocfg_reg88, &EV300_iocfg_reg89,
    &EV300_iocfg_reg90, &EV300_iocfg_reg91,
    &EV300_iocfg_reg92, 0,
};

MUXCTRL(_8EV300_iocfg_reg0, 0x100C0000, "GPIO0_1", "UART0_RXD")
MUXCTRL(_8EV300_iocfg_reg1, 0x100C0004, "GPIO0_2", "UART0_TXD")
MUXCTRL(_8EV300_iocfg_reg2, 0x100C0008, "GPIO0_0", "UPDATE_MODE")
MUXCTRL(_8EV300_iocfg_reg3, 0x100C000C, "GPIO0_3", "PWM0", "UART1_TXD",
        "I2C1_SCL")
MUXCTRL(_8EV300_iocfg_reg4, 0x100C0010, "GPIO0_4", "PWM1", "UART1_RXD",
        "I2C1_SDA")
MUXCTRL(_8EV300_iocfg_reg5, 0x100C0014, "EMMC_CLK", "SFC_CLK",
        "SFC_DEVICE_MODE")
MUXCTRL(_8EV300_iocfg_reg6, 0x100C0018, "EMMC_CMD", "SFC_MOSI_IO0")
MUXCTRL(_8EV300_iocfg_reg7, 0x100C001C, "EMMC_DATA0", "SFC_MISO_IO1")
MUXCTRL(_8EV300_iocfg_reg8, 0x100C0020, "EMMC_DATA3", "SFC_WP_IO2")
MUXCTRL(_8EV300_iocfg_reg9, 0x100C0024, "EMMC_DATA2", "SFC_HOLD_IO3")
MUXCTRL(_8EV300_iocfg_reg10, 0x100C0028, "EMMC_DATA1", "SFC_CSN")
MUXCTRL(_8EV300_iocfg_reg11, 0x100C002C, "SYS_RSTN_OUT")
MUXCTRL(_8EV300_iocfg_reg12, 0x100C0040, "GPIO4_0", "SDIO0_CCLK_OUT",
        "JTAG_TCK", "EMMC_CLK", "SDIO1_CCLK_OUT", "reserved",
        "VO_BT1120_DATA10", "SFC_INPUT_SEL")
MUXCTRL(_8EV300_iocfg_reg13, 0x100C0044, "GPIO4_1", "SDIO0_CCMD", "reserved",
        "EMMC_CMD", "SDIO1_CCMD", "reserved", "VO_BT1120_DATA11")
MUXCTRL(_8EV300_iocfg_reg14, 0x100C0048, "GPIO4_2", "SDIO0_CDATA0", "JTAG_TMS",
        "EMMC_DATA1", "SDIO1_CDATA3", "reserved", "VO_BT1120_DATA12")
MUXCTRL(_8EV300_iocfg_reg15, 0x100C004C, "GPIO4_3", "SDIO0_CDATA1", "JTAG_TDO",
        "EMMC_DATA2", "SDIO1_CDATA2", "reserved", "VO_BT1120_DATA13")
MUXCTRL(_8EV300_iocfg_reg16, 0x100C0050, "GPIO4_4", "SDIO0_CDATA2", "JTAG_TDI",
        "EMMC_DATA3", "SDIO1_CDATA1", "reserved", "VO_BT1120_DATA14")
MUXCTRL(_8EV300_iocfg_reg17, 0x100C0054, "GPIO4_5", "SDIO0_CDATA3",
        "JTAG_TRSTN", "EMMC_DATA0", "SDIO1_CDATA0", "reserved",
        "VO_BT1120_DATA15")
MUXCTRL(_8EV300_iocfg_reg18, 0x100C005C, "GPIO4_7", "SDIO0_CARD_DETECT",
        "reserved", "EMMC_RST_N")
MUXCTRL(_8EV300_iocfg_reg19, 0x112C0000, "MIPI_RX_CK0N", "reserved", "VI_CLK")
MUXCTRL(_8EV300_iocfg_reg20, 0x112C0004, "MIPI_RX_CK0P", "reserved", "VI_DATA7")
MUXCTRL(_8EV300_iocfg_reg21, 0x112C0008, "MIPI_RX_D0N", "reserved", "VI_DATA8")
MUXCTRL(_8EV300_iocfg_reg22, 0x112C000C, "MIPI_RX_D0P", "reserved", "VI_DATA9")
MUXCTRL(_8EV300_iocfg_reg23, 0x112C0010, "MIPI_RX_D2N", "reserved", "VI_DATA11")
MUXCTRL(_8EV300_iocfg_reg24, 0x112C0014, "MIPI_RX_D2P", "reserved", "VI_DATA10")
MUXCTRL(_8EV300_iocfg_reg25, 0x112C0028, "TEST_CLK", "SENSOR_CLK", "VI_DATA6",
        "reserved", "GPIO5_4")
MUXCTRL(_8EV300_iocfg_reg26, 0x112C002C, "GPIO5_5", "SENSOR_RSTN", "VI_DATA4")
MUXCTRL(_8EV300_iocfg_reg27, 0x112C0030, "GPIO5_6", "I2C0_SDA", "VI_DATA3")
MUXCTRL(_8EV300_iocfg_reg28, 0x112C0034, "GPIO5_7", "I2C0_SCL", "VI_DATA5")
MUXCTRL(_8EV300_iocfg_reg29, 0x112C0038, "GPIO6_2", "I2C2_SDA", "VI_DATA2",
        "reserved", "reserved", "reserved", "reserved", "SPI0_SDO")
MUXCTRL(_8EV300_iocfg_reg30, 0x112C003C, "GPIO6_3", "I2C2_SCL", "VI_DATA1",
        "reserved", "reserved", "reserved", "reserved", "SPI0_SCLK")
MUXCTRL(_8EV300_iocfg_reg31, 0x112C0040, "GPIO5_0", "reserved", "VI_DATA0",
        "reserved", "reserved", "reserved", "reserved", "SPI0_CSN")
MUXCTRL(_8EV300_iocfg_reg32, 0x112C0044, "GPIO5_1", "reserved", "TEST_MODE")
MUXCTRL(_8EV300_iocfg_reg33, 0x112C0048, "GPIO8_7", "BOOT_SEL1", "SENSOR_RSTN",
        "VO_BT656_CLK", "SDIO1_CCLK_OUT", "LCD_CLK", "VO_BT1120_CLK",
        "SPI1_SCLK")
MUXCTRL(_8EV300_iocfg_reg34, 0x112C004C, "GPIO8_5", "reserved", "VI_HS",
        "VO_BT656_DATA0", "SDIO1_CCMD", "LCD_HS", "VO_BT1120_DATA8", "SPI1_SDI")
MUXCTRL(_8EV300_iocfg_reg35, 0x112C0050, "GPIO8_6", "reserved", "VI_VS",
        "VO_BT656_DATA1", "reserved", "LCD_VS", "VO_BT1120_DATA9", "SPI1_SDO")
MUXCTRL(_8EV300_iocfg_reg36, 0x112C0054, "GPIO8_4", "BOOT_SEL0", "SENSOR_CLK",
        "PWM2", "reserved", "LCD_DE", "reserved", "SPI1_CSN0")
MUXCTRL(_8EV300_iocfg_reg37, 0x112C0058, "GPIO7_0", "reserved", "I2C2_SCL",
        "VO_BT656_DATA4", "SDIO1_CDATA3", "LCD_DATA4", "VO_BT1120_DATA4",
        "SPI1_CSN1")
MUXCTRL(_8EV300_iocfg_reg38, 0x112C005C, "GPIO7_1", "reserved", "I2C2_SDA",
        "VO_BT656_DATA5", "SDIO1_CDATA2", "LCD_DATA5", "VO_BT1120_DATA5")
MUXCTRL(_8EV300_iocfg_reg39, 0x112C0060, "GPIO7_2", "reserved", "I2C0_SDA",
        "VO_BT656_DATA6", "SDIO1_CDATA1", "LCD_DATA6", "VO_BT1120_DATA6")
MUXCTRL(_8EV300_iocfg_reg40, 0x112C0064, "GPIO7_3", "reserved", "I2C0_SCL",
        "VO_BT656_DATA7", "SDIO1_CDATA0", "LCD_DATA7", "VO_BT1120_DATA7")
MUXCTRL(_8EV300_iocfg_reg41, 0x112C0068, "GPIO6_7", "reserved", "reserved",
        "VO_BT656_DATA3", "reserved", "LCD_DATA3", "VO_BT1120_DATA3",
        "SPI0_CSN")
MUXCTRL(_8EV300_iocfg_reg42, 0x112C006C, "GPIO6_6", "SFC_BOOT_MODE", "PWM3",
        "VO_BT656_DATA2", "reserved", "LCD_DATA2", "VO_BT1120_DATA2",
        "SPI0_SDO")
MUXCTRL(_8EV300_iocfg_reg43, 0x112C0070, "GPIO6_5", "reserved", "UART1_RXD",
        "reserved", "reserved", "LCD_DATA1", "VO_BT1120_DATA1", "SPI0_SDI")
MUXCTRL(_8EV300_iocfg_reg44, 0x112C0074, "GPIO6_4", "reserved", "UART1_TXD",
        "reserved", "reserved", "LCD_DATA0", "VO_BT1120_DATA0", "SPI0_SCLK")
MUXCTRL(_8EV300_iocfg_reg45, 0x120C0000, "GPIO1_0", "LSADC_CH0")
MUXCTRL(_8EV300_iocfg_reg46, 0x120C0004, "GPIO1_1", "LSADC_CH1")
MUXCTRL(_8EV300_iocfg_reg47, 0x120C0010, "JTAG_TRSTN", "SPI1_CSN0", "GPIO1_4",
        "reserved", "UART2_RXD", "I2S_MCLK")
MUXCTRL(_8EV300_iocfg_reg48, 0x120C0014, "JTAG_TCK", "SPI1_SCLK", "GPIO1_5",
        "reserved", "UART2_TXD", "I2S_BCLK")
MUXCTRL(_8EV300_iocfg_reg49, 0x120C0018, "JTAG_TMS", "SPI1_SDI", "GPIO1_6",
        "PWM2", "UART2_CTSN", "I2S_WS")
MUXCTRL(_8EV300_iocfg_reg50, 0x120C001C, "JTAG_TDO", "SPI1_SDO", "GPIO1_7",
        "reserved", "UART2_RTSN", "I2S_SD_RX")
MUXCTRL(_8EV300_iocfg_reg51, 0x120C0020, "JTAG_TDI", "SPI1_CSN1", "GPIO2_0",
        "SDIO0_CARD_POWER_EN_N", "PWM3", "I2S_SD_TX")
MUXCTRL(_8EV300_iocfg_reg52, 0x120F0010, "PWR_RSTN")
MUXCTRL(_8EV300_iocfg_reg53, 0x120F0014, "PWR_SEQ")
MUXCTRL(_8EV300_iocfg_reg54, 0x120F0018, "PWR_BUTTON")
MUXCTRL(_8EV300_iocfg_reg55, 0x120F0020, "PWR_WAKEUP")

static const muxctrl_reg_t *_8EV300regs[] = {
    &_8EV300_iocfg_reg0,  &_8EV300_iocfg_reg1,  &_8EV300_iocfg_reg2,
    &_8EV300_iocfg_reg3,  &_8EV300_iocfg_reg4,  &_8EV300_iocfg_reg5,
    &_8EV300_iocfg_reg6,  &_8EV300_iocfg_reg7,  &_8EV300_iocfg_reg8,
    &_8EV300_iocfg_reg9,  &_8EV300_iocfg_reg10, &_8EV300_iocfg_reg11,
    &_8EV300_iocfg_reg12, &_8EV300_iocfg_reg13, &_8EV300_iocfg_reg14,
    &_8EV300_iocfg_reg15, &_8EV300_iocfg_reg16, &_8EV300_iocfg_reg17,
    &_8EV300_iocfg_reg18, &_8EV300_iocfg_reg19, &_8EV300_iocfg_reg20,
    &_8EV300_iocfg_reg21, &_8EV300_iocfg_reg22, &_8EV300_iocfg_reg23,
    &_8EV300_iocfg_reg24, &_8EV300_iocfg_reg25, &_8EV300_iocfg_reg26,
    &_8EV300_iocfg_reg27, &_8EV300_iocfg_reg28, &_8EV300_iocfg_reg29,
    &_8EV300_iocfg_reg30, &_8EV300_iocfg_reg31, &_8EV300_iocfg_reg32,
    &_8EV300_iocfg_reg33, &_8EV300_iocfg_reg34, &_8EV300_iocfg_reg35,
    &_8EV300_iocfg_reg36, &_8EV300_iocfg_reg37, &_8EV300_iocfg_reg38,
    &_8EV300_iocfg_reg39, &_8EV300_iocfg_reg40, &_8EV300_iocfg_reg41,
    &_8EV300_iocfg_reg42, &_8EV300_iocfg_reg43, &_8EV300_iocfg_reg44,
    &_8EV300_iocfg_reg45, &_8EV300_iocfg_reg46, &_8EV300_iocfg_reg47,
    &_8EV300_iocfg_reg48, &_8EV300_iocfg_reg49, &_8EV300_iocfg_reg50,
    &_8EV300_iocfg_reg51, &_8EV300_iocfg_reg52, &_8EV300_iocfg_reg53,
    &_8EV300_iocfg_reg54, &_8EV300_iocfg_reg55, 0,
};

MUXCTRL(DV200_iocfg_reg0, 0x100C0000, "GPIO0_1", "UART0_RXD")
MUXCTRL(DV200_iocfg_reg1, 0x100C0004, "GPIO0_2", "UART0_TXD")
MUXCTRL(DV200_iocfg_reg2, 0x100C0008, "GPIO0_0", "UPDATE_MODE")
MUXCTRL(DV200_iocfg_reg3, 0x100C000C, "GPIO0_3", "PWM0", "UART1_TXD",
        "I2C1_SCL")
MUXCTRL(DV200_iocfg_reg4, 0x100C0010, "GPIO0_4", "PWM1", "UART1_RXD",
        "I2C1_SDA")
MUXCTRL(DV200_iocfg_reg5, 0x100C0014, "EMMC_CLK", "SFC_CLK", "SFC_DEVICE_MODE")
MUXCTRL(DV200_iocfg_reg6, 0x100C0018, "EMMC_CMD", "SFC_MOSI_IO0")
MUXCTRL(DV200_iocfg_reg7, 0x100C001C, "EMMC_DATA0", "SFC_MISO_IO1")
MUXCTRL(DV200_iocfg_reg8, 0x100C0020, "EMMC_DATA3", "SFC_WP_IO2")
MUXCTRL(DV200_iocfg_reg9, 0x100C0024, "EMMC_DATA2", "SFC_HOLD_IO3")
MUXCTRL(DV200_iocfg_reg10, 0x100C0028, "EMMC_DATA1", "SFC_CSN")
MUXCTRL(DV200_iocfg_reg11, 0x100C002C, "SYS_RSTN_OUT", "WDG_RSTN")
MUXCTRL(DV200_iocfg_reg12, 0x100C0030, "GPIO3_4", "reserved", "reserved",
        "EMMC_DATA4")
MUXCTRL(DV200_iocfg_reg13, 0x100C0034, "GPIO3_5", "reserved", "reserved",
        "EMMC_DATA5")
MUXCTRL(DV200_iocfg_reg14, 0x100C0038, "GPIO3_6", "reserved", "reserved",
        "EMMC_DATA6")
MUXCTRL(DV200_iocfg_reg15, 0x100C003C, "GPIO3_7", "reserved", "reserved",
        "EMMC_DATA7")
MUXCTRL(DV200_iocfg_reg16, 0x100C0040, "GPIO4_0", "SDIO0_CCLK_OUT", "JTAG_TCK",
        "EMMC_CLK", "SDIO1_CCLK_OUT", "reserved", "reserved", "SFC_INPUT_SEL")
MUXCTRL(DV200_iocfg_reg17, 0x100C0044, "GPIO4_1", "SDIO0_CCMD", "reserved",
        "EMMC_CMD", "SDIO1_CCMD")
MUXCTRL(DV200_iocfg_reg18, 0x100C0048, "GPIO4_2", "SDIO0_CDATA0", "JTAG_TMS",
        "EMMC_DATA1", "SDIO1_CDATA3")
MUXCTRL(DV200_iocfg_reg19, 0x100C004C, "GPIO4_3", "SDIO0_CDATA1", "JTAG_TDO",
        "EMMC_DATA2", "SDIO1_CDATA2")
MUXCTRL(DV200_iocfg_reg20, 0x100C0050, "GPIO4_4", "SDIO0_CDATA2", "JTAG_TDI",
        "EMMC_DATA3", "SDIO1_CDATA1")
MUXCTRL(DV200_iocfg_reg21, 0x100C0054, "GPIO4_5", "SDIO0_CDATA3", "JTAG_TRSTN",
        "EMMC_DATA0", "SDIO1_CDATA0")
MUXCTRL(DV200_iocfg_reg22, 0x100C0058, "GPIO4_6", "SDIO0_CARD_POWER_EN_N",
        "reserved", "EMMC_DS")
MUXCTRL(DV200_iocfg_reg23, 0x100C005C, "GPIO4_7", "SDIO0_CARD_DETECT",
        "reserved", "EMMC_RST_N")
MUXCTRL(DV200_iocfg_reg24, 0x100C0060, "GPIO2_1", "SFC_CLK", "reserved",
        "reserved", "SDIO1_CCLK_OUT")
MUXCTRL(DV200_iocfg_reg25, 0x100C0064, "GPIO2_2", "SFC_WP_IO2", "reserved",
        "reserved", "SDIO1_CCMD")
MUXCTRL(DV200_iocfg_reg26, 0x100C0068, "GPIO3_0", "SFC_MOSI_IO0", "reserved",
        "reserved", "SDIO1_CDATA0")
MUXCTRL(DV200_iocfg_reg27, 0x100C006C, "GPIO3_1", "SFC_HOLD_IO3", "reserved",
        "reserved", "SDIO1_CDATA1")
MUXCTRL(DV200_iocfg_reg28, 0x100C0070, "GPIO3_2", "SFC_CSN", "reserved",
        "reserved", "SDIO1_CDATA2")
MUXCTRL(DV200_iocfg_reg29, 0x100C0074, "GPIO3_3", "SFC_MISO_IO1", "reserved",
        "reserved", "SDIO1_CDATA3")
MUXCTRL(DV200_iocfg_reg30, 0x100C0078, "GPIO0_5", "USB_OVRCUR")
MUXCTRL(DV200_iocfg_reg31, 0x100C007C, "GPIO0_6", "USB_VBUS")
MUXCTRL(DV200_iocfg_reg32, 0x100C0080, "GPIO0_7", "USB_PWREN")
MUXCTRL(DV200_iocfg_reg33, 0x100C0084, "GPIO2_4", "SPI1_SCLK")
MUXCTRL(DV200_iocfg_reg34, 0x100C0088, "GPIO2_5", "SPI1_SDO")
MUXCTRL(DV200_iocfg_reg35, 0x100C008C, "GPIO2_6", "SPI1_CSN0")
MUXCTRL(DV200_iocfg_reg36, 0x100C0090, "GPIO2_7", "SPI1_SDI")
MUXCTRL(DV200_iocfg_reg37, 0x100C0094, "RST_N")
MUXCTRL(DV200_iocfg_reg38, 0x100C0098, "POR_SEL")
MUXCTRL(DV200_iocfg_reg39, 0x100C009C, "GPIO9_0", "PWM2")
MUXCTRL(DV200_iocfg_reg40, 0x100C00A0, "GPIO9_1", "PWM3")
MUXCTRL(DV200_iocfg_reg41, 0x100C00A4, "GPIO2_3", "SVB_PWM")
MUXCTRL(DV200_iocfg_reg42, 0x112C0000, "MIPI_RX_CK0N", "VI_BT1120_DATA10",
        "VI_CLK")
MUXCTRL(DV200_iocfg_reg43, 0x112C0004, "MIPI_RX_CK0P", "VI_BT1120_DATA11",
        "VI_DATA7")
MUXCTRL(DV200_iocfg_reg44, 0x112C0008, "MIPI_RX_D0N", "VI_BT1120_DATA12",
        "reserved", "VI_DATA9")
MUXCTRL(DV200_iocfg_reg45, 0x112C000C, "MIPI_RX_D0P", "VI_BT1120_DATA13",
        "reserved", "VI_DATA8")
MUXCTRL(DV200_iocfg_reg46, 0x112C0010, "MIPI_RX_D2N", "VI_BT1120_DATA14",
        "reserved", "VI_DATA10")
MUXCTRL(DV200_iocfg_reg47, 0x112C0014, "MIPI_RX_D2P", "VI_BT1120_DATA15",
        "reserved", "VI_DATA11")
MUXCTRL(DV200_iocfg_reg48, 0x112C0018, "MIPI_RX_D1N", "VI_BT1120_DATA6",
        "reserved", "VI_DATA6")
MUXCTRL(DV200_iocfg_reg49, 0x112C001C, "MIPI_RX_D1P", "VI_BT1120_DATA7",
        "reserved", "VI_DATA4")
MUXCTRL(DV200_iocfg_reg50, 0x112C0020, "MIPI_RX_D3N", "VI_BT1120_DATA8",
        "reserved", "VI_DATA3")
MUXCTRL(DV200_iocfg_reg51, 0x112C0024, "MIPI_RX_D3P", "VI_BT1120_DATA9",
        "reserved", "VI_DATA5")
MUXCTRL(DV200_iocfg_reg52, 0x112C0028, "TEST_CLK", "SENSOR_CLK", "reserved",
        "reserved", "GPIO5_4")
MUXCTRL(DV200_iocfg_reg53, 0x112C002C, "GPIO5_5", "SENSOR_RSTN")
MUXCTRL(DV200_iocfg_reg54, 0x112C0030, "GPIO5_6", "I2C0_SDA")
MUXCTRL(DV200_iocfg_reg55, 0x112C0034, "GPIO5_7", "I2C0_SCL")
MUXCTRL(DV200_iocfg_reg56, 0x112C0038, "GPIO6_2", "I2C2_SDA", "reserved",
        "VI_HS", "reserved", "reserved", "reserved", "SPI0_SDO")
MUXCTRL(DV200_iocfg_reg57, 0x112C003C, "GPIO6_3", "I2C2_SCL", "reserved",
        "VI_VS", "reserved", "reserved", "reserved", "SPI0_SCLK")
MUXCTRL(DV200_iocfg_reg58, 0x112C0040, "GPIO5_0", "ETH_LINK_STA_LED",
        "reserved", "VI_DATA2", "reserved", "reserved", "reserved", "SPI0_CSN")
MUXCTRL(DV200_iocfg_reg59, 0x112C0044, "GPIO5_1", "ETH_LINK_ACT_LED",
        "TEST_MODE")
MUXCTRL(DV200_iocfg_reg60, 0x112C0048, "GPIO8_7", "BOOT_SEL1", "SENSOR_RSTN",
        "VO_BT656_CLK", "SDIO1_CCLK_OUT", "LCD_CLK", "VO_BT1120_CLK",
        "SPI1_SCLK")
MUXCTRL(DV200_iocfg_reg61, 0x112C004C, "GPIO8_5", "VI_BT1120_DATA0", "VI_HS",
        "VO_BT656_DATA0", "SDIO1_CCMD", "LCD_HS", "VO_BT1120_DATA8", "SPI1_SDI")
MUXCTRL(DV200_iocfg_reg62, 0x112C0050, "GPIO8_6", "VI_BT1120_DATA1", "VI_VS",
        "VO_BT656_DATA1", "reserved", "LCD_VS", "VO_BT1120_DATA9", "SPI1_SDO")
MUXCTRL(DV200_iocfg_reg63, 0x112C0054, "GPIO8_4", "BOOT_SEL0", "SENSOR_CLK",
        "PWM2", "reserved", "LCD_DE", "reserved", "SPI1_CSN0")
MUXCTRL(DV200_iocfg_reg64, 0x112C0058, "GPIO7_0", "VI_BT1120_DATA4", "I2C2_SCL",
        "VO_BT656_DATA4", "SDIO1_CDATA3", "LCD_DATA4", "VO_BT1120_DATA4",
        "SPI1_CSN1", "LCD_DATA3")
MUXCTRL(DV200_iocfg_reg65, 0x112C005C, "GPIO7_1", "VI_BT1120_DATA5", "I2C2_SDA",
        "VO_BT656_DATA5", "SDIO1_CDATA2", "LCD_DATA5", "VO_BT1120_DATA5",
        "VI_DATA0", "LCD_DATA2")
MUXCTRL(DV200_iocfg_reg66, 0x112C0060, "GPIO7_2", "VI_BT1120_CLK", "I2C0_SDA",
        "VO_BT656_DATA6", "SDIO1_CDATA1", "LCD_DATA6", "VO_BT1120_DATA6",
        "VI_DATA1", "LCD_DATA1")
MUXCTRL(DV200_iocfg_reg67, 0x112C0064, "GPIO7_3", "reserved", "I2C0_SCL",
        "VO_BT656_DATA7", "SDIO1_CDATA0", "LCD_DATA7", "VO_BT1120_DATA7",
        "VI_DATA2", "LCD_DATA0")
MUXCTRL(DV200_iocfg_reg68, 0x112C0068, "GPIO6_7", "VI_BT1120_DATA3", "reserved",
        "VO_BT656_DATA3", "LCD_DE", "LCD_DATA3", "VO_BT1120_DATA3", "SPI0_CSN",
        "LCD_DATA4")
MUXCTRL(DV200_iocfg_reg69, 0x112C006C, "GPIO6_6", "SFC_BOOT_MODE", "PWM3",
        "VO_BT656_DATA2", "LCD_VS", "LCD_DATA2", "VO_BT1120_DATA2", "SPI0_SDO",
        "LCD_DATA5")
MUXCTRL(DV200_iocfg_reg70, 0x112C0070, "GPIO6_5", "VI_BT1120_DATA2",
        "UART1_RXD", "reserved", "LCD_HS", "LCD_DATA1", "VO_BT1120_DATA1",
        "SPI0_SDI", "LCD_DATA6")
MUXCTRL(DV200_iocfg_reg71, 0x112C0074, "GPIO6_4", "reserved", "UART1_TXD",
        "reserved", "LCD_CLK", "LCD_DATA0", "VO_BT1120_DATA0", "SPI0_SCLK",
        "LCD_DATA7")
MUXCTRL(DV200_iocfg_reg72, 0x112C0078, "GPIO7_4", "UART1_TXD", "reserved",
        "reserved", "LCD_DATA0", "LCD_DATA8", "reserved", "reserved",
        "LCD_DATA15")
MUXCTRL(DV200_iocfg_reg73, 0x112C007C, "GPIO7_5", "UART1_RXD", "reserved",
        "reserved", "LCD_DATA1", "LCD_DATA9", "reserved", "reserved",
        "LCD_DATA14")
MUXCTRL(DV200_iocfg_reg74, 0x112C0080, "GPIO7_6", "UART1_CTSN", "reserved",
        "reserved", "LCD_DATA2", "LCD_DATA10", "VO_BT1120_DATA10", "reserved",
        "LCD_DATA13")
MUXCTRL(DV200_iocfg_reg75, 0x112C0084, "GPIO7_7", "UART1_RTSN", "reserved",
        "reserved", "LCD_DATA3", "LCD_DATA11", "VO_BT1120_DATA11", "reserved",
        "LCD_DATA12")
MUXCTRL(DV200_iocfg_reg76, 0x112C0088, "GPIO8_0", "reserved", "reserved",
        "reserved", "LCD_DATA4", "LCD_DATA12", "VO_BT1120_DATA12", "reserved",
        "LCD_DATA11")
MUXCTRL(DV200_iocfg_reg77, 0x112C008C, "GPIO8_1", "reserved", "reserved",
        "reserved", "LCD_DATA5", "LCD_DATA13", "VO_BT1120_DATA13", "reserved",
        "LCD_DATA10")
MUXCTRL(DV200_iocfg_reg78, 0x112C0090, "GPIO8_2", "reserved", "reserved",
        "reserved", "LCD_DATA6", "LCD_DATA14", "VO_BT1120_DATA14", "reserved",
        "LCD_DATA9")
MUXCTRL(DV200_iocfg_reg79, 0x112C0094, "GPIO8_3", "reserved", "reserved",
        "reserved", "LCD_DATA7", "LCD_DATA15", "VO_BT1120_DATA15", "reserved",
        "LCD_DATA8")
MUXCTRL(DV200_iocfg_reg80, 0x112C0098, "GPIO5_2", "FLASH_TRIG", "SENSOR_HS")
MUXCTRL(DV200_iocfg_reg81, 0x112C009C, "GPIO5_3", "SHUTTER_TRIG", "SENSOR_VS",
        "reserved", "SPI0_CSN")
MUXCTRL(DV200_iocfg_reg82, 0x112C00A0, "GPIO6_0", "I2C1_SDA", "reserved",
        "reserved", "SPI0_SDO")
MUXCTRL(DV200_iocfg_reg83, 0x112C00A4, "GPIO6_1", "I2C1_SCL", "reserved",
        "reserved", "SPI0_SCLK")
MUXCTRL(DV200_iocfg_reg84, 0x120C0000, "GPIO1_0", "LSADC_CH0")
MUXCTRL(DV200_iocfg_reg85, 0x120C0004, "GPIO1_1", "LSADC_CH1")
MUXCTRL(DV200_iocfg_reg86, 0x120C0008, "GPIO1_2", "LSADC_CH2")
MUXCTRL(DV200_iocfg_reg87, 0x120C000C, "GPIO1_3", "LSADC_CH3")
MUXCTRL(DV200_iocfg_reg88, 0x120C0010, "JTAG_TRSTN", "SPI1_CSN0", "GPIO1_4",
        "reserved", "UART2_RXD", "I2S_MCLK")
MUXCTRL(DV200_iocfg_reg89, 0x120C0014, "JTAG_TCK", "SPI1_SCLK", "GPIO1_5",
        "reserved", "UART2_TXD", "I2S_BCLK")
MUXCTRL(DV200_iocfg_reg90, 0x120C0018, "JTAG_TMS", "SPI1_SDI", "GPIO1_6",
        "PWM2", "UART2_CTSN", "I2S_WS")
MUXCTRL(DV200_iocfg_reg91, 0x120C001C, "JTAG_TDO", "SPI1_SDO", "GPIO1_7",
        "reserved", "UART2_RTSN", "I2S_SD_RX")
MUXCTRL(DV200_iocfg_reg92, 0x120C0020, "JTAG_TDI", "SPI1_CSN1", "GPIO2_0",
        "SDIO0_CARD_POWER_EN_N", "PWM3", "I2S_SD_TX")
MUXCTRL(DV200_iocfg_reg93, 0x120F0010, "PWR_RSTN")
MUXCTRL(DV200_iocfg_reg94, 0x120F0014, "PWR_SEQ")
MUXCTRL(DV200_iocfg_reg95, 0x120F0018, "PWR_BUTTON")
MUXCTRL(DV200_iocfg_reg96, 0x120F001C, "PWR_STARTUP")
MUXCTRL(DV200_iocfg_reg97, 0x120F0020, "PWR_WAKEUP")
MUXCTRL(DV200_iocfg_reg98, 0x120F0024, "PWR_EN")

static const muxctrl_reg_t *DV200regs[] = {
    &DV200_iocfg_reg0,  &DV200_iocfg_reg1,
    &DV200_iocfg_reg2,  &DV200_iocfg_reg3,
    &DV200_iocfg_reg4,  &DV200_iocfg_reg5,
    &DV200_iocfg_reg6,  &DV200_iocfg_reg7,
    &DV200_iocfg_reg8,  &DV200_iocfg_reg9,
    &DV200_iocfg_reg10, &DV200_iocfg_reg11,
    &DV200_iocfg_reg12, &DV200_iocfg_reg13,
    &DV200_iocfg_reg14, &DV200_iocfg_reg15,
    &DV200_iocfg_reg16, &DV200_iocfg_reg17,
    &DV200_iocfg_reg18, &DV200_iocfg_reg19,
    &DV200_iocfg_reg20, &DV200_iocfg_reg21,
    &DV200_iocfg_reg22, &DV200_iocfg_reg23,
    &DV200_iocfg_reg24, &DV200_iocfg_reg25,
    &DV200_iocfg_reg26, &DV200_iocfg_reg27,
    &DV200_iocfg_reg28, &DV200_iocfg_reg29,
    &DV200_iocfg_reg30, &DV200_iocfg_reg31,
    &DV200_iocfg_reg32, &DV200_iocfg_reg33,
    &DV200_iocfg_reg34, &DV200_iocfg_reg35,
    &DV200_iocfg_reg36, &DV200_iocfg_reg37,
    &DV200_iocfg_reg38, &DV200_iocfg_reg39,
    &DV200_iocfg_reg40, &DV200_iocfg_reg41,
    &DV200_iocfg_reg42, &DV200_iocfg_reg43,
    &DV200_iocfg_reg44, &DV200_iocfg_reg45,
    &DV200_iocfg_reg46, &DV200_iocfg_reg47,
    &DV200_iocfg_reg48, &DV200_iocfg_reg49,
    &DV200_iocfg_reg50, &DV200_iocfg_reg51,
    &DV200_iocfg_reg52, &DV200_iocfg_reg53,
    &DV200_iocfg_reg54, &DV200_iocfg_reg55,
    &DV200_iocfg_reg56, &DV200_iocfg_reg57,
    &DV200_iocfg_reg58, &DV200_iocfg_reg59,
    &DV200_iocfg_reg60, &DV200_iocfg_reg61,
    &DV200_iocfg_reg62, &DV200_iocfg_reg63,
    &DV200_iocfg_reg64, &DV200_iocfg_reg65,
    &DV200_iocfg_reg66, &DV200_iocfg_reg67,
    &DV200_iocfg_reg68, &DV200_iocfg_reg69,
    &DV200_iocfg_reg70, &DV200_iocfg_reg71,
    &DV200_iocfg_reg72, &DV200_iocfg_reg73,
    &DV200_iocfg_reg74, &DV200_iocfg_reg75,
    &DV200_iocfg_reg76, &DV200_iocfg_reg77,
    &DV200_iocfg_reg78, &DV200_iocfg_reg79,
    &DV200_iocfg_reg80, &DV200_iocfg_reg81,
    &DV200_iocfg_reg82, &DV200_iocfg_reg83,
    &DV200_iocfg_reg84, &DV200_iocfg_reg85,
    &DV200_iocfg_reg86, &DV200_iocfg_reg87,
    &DV200_iocfg_reg88, &DV200_iocfg_reg89,
    &DV200_iocfg_reg90, &DV200_iocfg_reg91,
    &DV200_iocfg_reg92, &DV200_iocfg_reg93,
    &DV200_iocfg_reg94, &DV200_iocfg_reg95,
    &DV200_iocfg_reg96, &DV200_iocfg_reg97,
    &DV200_iocfg_reg98, 0,
};

MUXCTRL(DV100_muxctrl_reg0, 0x120F0000, "GPIO2_4", "VGA_HS")
MUXCTRL(DV100_muxctrl_reg1, 0x120F0004, "GPIO2_5", "VGA_VS")
MUXCTRL(DV100_muxctrl_reg2, 0x120F0008, "PWM_SVB_CORE", "GPIO2_6")
MUXCTRL(DV100_muxctrl_reg3, 0x120F000C, "PWM_SVB_CPU", "GPIO2_7")
MUXCTRL(DV100_muxctrl_reg4, 0x120F0010, "GPIO5_7", "PWM_FREE")
MUXCTRL(DV100_muxctrl_reg5, 0x120F0014, "GPIO3_0", "I2C_SDA")
MUXCTRL(DV100_muxctrl_reg6, 0x120F0018, "GPIO3_1", "I2C_SCL")
MUXCTRL(DV100_muxctrl_reg7, 0x120F001C, "GPIO4_0", "UART1_RXD")
MUXCTRL(DV100_muxctrl_reg8, 0x120F0020, "GPIO4_1", "UART1_TXD")
MUXCTRL(DV100_muxctrl_reg9, 0x120F0024, "GPIO4_2", "UART1_RTSN")
MUXCTRL(DV100_muxctrl_reg10, 0x120F0028, "GPIO4_3", "UART1_CTSN")
MUXCTRL(DV100_muxctrl_reg11, 0x120F002C, "GPIO4_4", "UART2_RXD")
MUXCTRL(DV100_muxctrl_reg12, 0x120F0030, "GPIO4_5", "UART2_TXD")
MUXCTRL(DV100_muxctrl_reg13, 0x120F0034, "GPIO4_6", "ETH_LINK_LED")
MUXCTRL(DV100_muxctrl_reg14, 0x120F0038, "GPIO4_7", "ETH_SPD_LED")
MUXCTRL(DV100_muxctrl_reg15, 0x120F003C, "GPIO3_2", "IR_IN")
MUXCTRL(DV100_muxctrl_reg16, 0x120F0040, "GPIO5_0", "reserved", "reserved",
        "I2S_SD_RX")
MUXCTRL(DV100_muxctrl_reg17, 0x120F0044, "GPIO5_1", "reserved", "reserved",
        "I2S_MCLK")
MUXCTRL(DV100_muxctrl_reg18, 0x120F0048, "GPIO5_2", "reserved", "reserved",
        "I2S_WS")
MUXCTRL(DV100_muxctrl_reg19, 0x120F004C, "GPIO5_3", "reserved", "reserved",
        "I2S_BCLK")
MUXCTRL(DV100_muxctrl_reg20, 0x120F0050, "GPIO5_4", "reserved", "reserved",
        "I2S_SD_TX")
MUXCTRL(DV100_muxctrl_reg21, 0x120F0054, "GPIO5_5", "USB2_PWREN0")
MUXCTRL(DV100_muxctrl_reg22, 0x120F0058, "GPIO5_6", "USB2_PWREN1")
MUXCTRL(DV100_muxctrl_reg23, 0x120F005C, "GPIO3_3", "HDMI_HOTPLUG")
MUXCTRL(DV100_muxctrl_reg24, 0x120F0060, "GPIO3_4", "HDMI_SDA")
MUXCTRL(DV100_muxctrl_reg25, 0x120F0064, "GPIO3_5", "HDMI_SCL")
MUXCTRL(DV100_muxctrl_reg26, 0x120F0068, "GPIO3_6", "SATA_LED_N")
MUXCTRL(DV100_muxctrl_reg27, 0x120F006C, "GPIO0_0", "MII_RXDV")
MUXCTRL(DV100_muxctrl_reg28, 0x120F0070, "GPIO0_1", "MII_RXD3", "I2S_WS")
MUXCTRL(DV100_muxctrl_reg29, 0x120F0074, "GPIO0_2", "MII_RXD2")
MUXCTRL(DV100_muxctrl_reg30, 0x120F0078, "GPIO0_3", "MII_RXD1", "I2S_BCLK")
MUXCTRL(DV100_muxctrl_reg31, 0x120F007C, "GPIO0_4", "MII_RXD0", "I2S_MCLK")
MUXCTRL(DV100_muxctrl_reg32, 0x120F0080, "GPIO0_5", "MII_RXCK")
MUXCTRL(DV100_muxctrl_reg33, 0x120F0084, "GPIO0_6", "MII_TXEN")
MUXCTRL(DV100_muxctrl_reg34, 0x120F0088, "GPIO0_7", "MII_TXD3")
MUXCTRL(DV100_muxctrl_reg35, 0x120F008C, "GPIO1_0", "MII_TXD2")
MUXCTRL(DV100_muxctrl_reg36, 0x120F0090, "GPIO1_1", "MII_TXD1", "I2S_SD_RX")
MUXCTRL(DV100_muxctrl_reg37, 0x120F0094, "GPIO1_2", "MII_TXD0", "I2S_SD_TX")
MUXCTRL(DV100_muxctrl_reg38, 0x120F0098, "GPIO1_3", "MII_TXCK", "RMII_CLK")
MUXCTRL(DV100_muxctrl_reg39, 0x120F009C, "GPIO1_4", "MII_CRS")
MUXCTRL(DV100_muxctrl_reg40, 0x120F00A0, "GPIO1_5", "MII_COL")
MUXCTRL(DV100_muxctrl_reg41, 0x120F00A4, "GPIO1_6", "MII_RXER")
MUXCTRL(DV100_muxctrl_reg42, 0x120F00A8, "GPIO1_7", "MII_TXER")
MUXCTRL(DV100_muxctrl_reg43, 0x120F00AC, "TEST_CLK", "EPHY_CLK", "GPIO2_0")
MUXCTRL(DV100_muxctrl_reg44, 0x120F00B0, "GPIO2_1", "EPHY_RSTN")
MUXCTRL(DV100_muxctrl_reg45, 0x120F00B4, "GPIO2_2", "MDCK")
MUXCTRL(DV100_muxctrl_reg46, 0x120F00B8, "GPIO2_3", "MDIO")

static const muxctrl_reg_t *DV100regs[] = {
    &DV100_muxctrl_reg0,  &DV100_muxctrl_reg1,  &DV100_muxctrl_reg2,
    &DV100_muxctrl_reg3,  &DV100_muxctrl_reg4,  &DV100_muxctrl_reg5,
    &DV100_muxctrl_reg6,  &DV100_muxctrl_reg7,  &DV100_muxctrl_reg8,
    &DV100_muxctrl_reg9,  &DV100_muxctrl_reg10, &DV100_muxctrl_reg11,
    &DV100_muxctrl_reg12, &DV100_muxctrl_reg13, &DV100_muxctrl_reg14,
    &DV100_muxctrl_reg15, &DV100_muxctrl_reg16, &DV100_muxctrl_reg17,
    &DV100_muxctrl_reg18, &DV100_muxctrl_reg19, &DV100_muxctrl_reg20,
    &DV100_muxctrl_reg21, &DV100_muxctrl_reg22, &DV100_muxctrl_reg23,
    &DV100_muxctrl_reg24, &DV100_muxctrl_reg25, &DV100_muxctrl_reg26,
    &DV100_muxctrl_reg27, &DV100_muxctrl_reg28, &DV100_muxctrl_reg29,
    &DV100_muxctrl_reg30, &DV100_muxctrl_reg31, &DV100_muxctrl_reg32,
    &DV100_muxctrl_reg33, &DV100_muxctrl_reg34, &DV100_muxctrl_reg35,
    &DV100_muxctrl_reg36, &DV100_muxctrl_reg37, &DV100_muxctrl_reg38,
    &DV100_muxctrl_reg39, &DV100_muxctrl_reg40, &DV100_muxctrl_reg41,
    &DV100_muxctrl_reg42, &DV100_muxctrl_reg43, &DV100_muxctrl_reg44,
    &DV100_muxctrl_reg45, &DV100_muxctrl_reg46, 0,
};

MUXCTRL(RCV100_muxctrl_reg0, 0x120F0000, "GPIO5_7", "reserved", "reserved",
        "RGMII1_TXER")
MUXCTRL(RCV100_muxctrl_reg1, 0x120F0004, "GPIO1_0", "reserved", "reserved",
        "EPHY1_CLK")
MUXCTRL(RCV100_muxctrl_reg2, 0x120F0008, "GPIO1_1", "reserved", "reserved",
        "RGMII1_TXD2")
MUXCTRL(RCV100_muxctrl_reg3, 0x120F000C, "GPIO1_2", "reserved", "reserved",
        "RGMII1_TXD3")
MUXCTRL(RCV100_muxctrl_reg4, 0x120F0010, "GPIO1_3", "reserved", "reserved",
        "RGMII1_TXD1")
MUXCTRL(RCV100_muxctrl_reg5, 0x120F0014, "GPIO1_4", "reserved", "reserved",
        "RGMII1_TXCKOUT", "MII1_TXCK", "RMII1_CLK")
MUXCTRL(RCV100_muxctrl_reg6, 0x120F0018, "GPIO1_5", "reserved", "reserved",
        "RGMII1_TXD0")
MUXCTRL(RCV100_muxctrl_reg7, 0x120F001C, "GPIO1_6", "reserved", "reserved",
        "RGMII1_TXEN")
MUXCTRL(RCV100_muxctrl_reg8, 0x120F0020, "GPIO1_7", "reserved", "reserved",
        "RGMII1_RXER")
MUXCTRL(RCV100_muxctrl_reg9, 0x120F0024, "GPIO10_6", "reserved", "reserved",
        "RGMII1_RXCK")
MUXCTRL(RCV100_muxctrl_reg10, 0x120F0028, "GPIO2_0", "reserved", "reserved",
        "MDCK1")
MUXCTRL(RCV100_muxctrl_reg11, 0x120F002C, "GPIO2_1", "reserved", "reserved",
        "MDIO1")
MUXCTRL(RCV100_muxctrl_reg12, 0x120F0030, "GPIO2_2", "reserved", "reserved",
        "RGMII1_CRS")
MUXCTRL(RCV100_muxctrl_reg13, 0x120F0034, "GPIO2_3", "reserved", "reserved",
        "EPHY1_RSTN")
MUXCTRL(RCV100_muxctrl_reg14, 0x120F0038, "GPIO2_4", "reserved", "reserved",
        "RGMII1_RXD3")
MUXCTRL(RCV100_muxctrl_reg15, 0x120F003C, "GPIO2_5", "reserved", "reserved",
        "RGMII1_RXD2")
MUXCTRL(RCV100_muxctrl_reg16, 0x120F0040, "GPIO2_6", "reserved", "reserved",
        "RGMII1_RXD0")
MUXCTRL(RCV100_muxctrl_reg17, 0x120F0044, "GPIO2_7", "reserved", "reserved",
        "RGMII1_RXD1")
MUXCTRL(RCV100_muxctrl_reg18, 0x120F0048, "GPIO6_0", "reserved", "reserved",
        "RGMII1_RXDV")
MUXCTRL(RCV100_muxctrl_reg20, 0x120F0050, "GPIO3_0", "reserved", "reserved",
        "RGMII1_COL")
MUXCTRL(RCV100_muxctrl_reg38, 0x120F0098, "GPIO11_6", "VGA_HS")
MUXCTRL(RCV100_muxctrl_reg39, 0x120F009C, "GPIO11_3", "VGA_VS")
MUXCTRL(RCV100_muxctrl_reg43, 0x120F00AC, "GPIO9_3", "I2S1_BCLK_RX",
        "I2S2_MCLK")
MUXCTRL(RCV100_muxctrl_reg44, 0x120F00B0, "GPIO9_4", "I2S1_WS_RX")
MUXCTRL(RCV100_muxctrl_reg45, 0x120F00B4, "GPIO9_5", "I2S1_SD_RX")
MUXCTRL(RCV100_muxctrl_reg46, 0x120F00B8, "GPIO9_6", "I2S2_BCLK_TX")
MUXCTRL(RCV100_muxctrl_reg47, 0x120F00BC, "GPIO9_7", "I2S2_WS_TX")
MUXCTRL(RCV100_muxctrl_reg48, 0x120F00C0, "GPIO5_4", "I2S2_SD_TX")
MUXCTRL(RCV100_muxctrl_reg49, 0x120F00C4, "TEST_CLK", "SPI_SCLK", "GPIO5_0")
MUXCTRL(RCV100_muxctrl_reg50, 0x120F00C8, "GPIO5_1", "SPI_MOSI")
MUXCTRL(RCV100_muxctrl_reg51, 0x120F00CC, "GPIO5_2", "SPI_MISO")
MUXCTRL(RCV100_muxctrl_reg52, 0x120F00D0, "GPIO5_3", "SPI_CSN0")
MUXCTRL(RCV100_muxctrl_reg53, 0x120F00D4, "GPIO8_7", "SPI_CSN1")
MUXCTRL(RCV100_muxctrl_reg54, 0x120F00D8, "PWM_OUT0", "GPIO5_5")
MUXCTRL(RCV100_muxctrl_reg55, 0x120F00DC, "PWM_OUT1", "GPIO5_6")
MUXCTRL(RCV100_muxctrl_reg56, 0x120F00E0, "GPIO12_6", "I2C_SDA")
MUXCTRL(RCV100_muxctrl_reg57, 0x120F00E4, "GPIO12_7", "I2C_SCL")
MUXCTRL(RCV100_muxctrl_reg58, 0x120F00E8, "UART0_RXD", "GPIO10_7")
MUXCTRL(RCV100_muxctrl_reg59, 0x120F00EC, "UART0_TXD", "GPIO12_5")
MUXCTRL(RCV100_muxctrl_reg60, 0x120F00F0, "UART0_CTSN", "GPIO6_2")
MUXCTRL(RCV100_muxctrl_reg61, 0x120F00F4, "UART0_RTSN", "GPIO6_3")
MUXCTRL(RCV100_muxctrl_reg62, 0x120F00F8, "GPIO6_5", "UART1_RXD")
MUXCTRL(RCV100_muxctrl_reg63, 0x120F00FC, "GPIO6_7", "UART1_TXD")
MUXCTRL(RCV100_muxctrl_reg64, 0x120F0100, "GPIO11_4", "UART2_RXD")
MUXCTRL(RCV100_muxctrl_reg65, 0x120F0104, "GPIO11_5", "UART2_TXD")
MUXCTRL(RCV100_muxctrl_reg66, 0x120F0108, "GPIO7_0", "RGMII0_RXDV")
MUXCTRL(RCV100_muxctrl_reg67, 0x120F010C, "GPIO7_1", "RGMII0_RXD3")
MUXCTRL(RCV100_muxctrl_reg68, 0x120F0110, "GPIO7_2", "RGMII0_RXD2")
MUXCTRL(RCV100_muxctrl_reg69, 0x120F0114, "GPIO7_3", "RGMII0_RXD1")
MUXCTRL(RCV100_muxctrl_reg70, 0x120F0118, "GPIO7_4", "RGMII0_RXD0")
MUXCTRL(RCV100_muxctrl_reg71, 0x120F011C, "GPIO7_5", "RGMII0_RXCK")
MUXCTRL(RCV100_muxctrl_reg72, 0x120F0120, "GPIO7_6", "RGMII0_TXEN")
MUXCTRL(RCV100_muxctrl_reg73, 0x120F0124, "GPIO7_7", "RGMII0_TXD3")
MUXCTRL(RCV100_muxctrl_reg74, 0x120F0128, "GPIO8_0", "RGMII0_TXD2")
MUXCTRL(RCV100_muxctrl_reg75, 0x120F012C, "GPIO8_1", "RGMII0_TXD1")
MUXCTRL(RCV100_muxctrl_reg76, 0x120F0130, "GPIO8_2", "RGMII0_TXD0")
MUXCTRL(RCV100_muxctrl_reg77, 0x120F0134, "GPIO8_3", "RGMII0_TXCKOUT",
        "MII0_TXCK", "RMII0_CLK")
MUXCTRL(RCV100_muxctrl_reg78, 0x120F0138, "GPIO8_4", "RGMII0_CRS")
MUXCTRL(RCV100_muxctrl_reg79, 0x120F013C, "GPIO8_5", "RGMII0_COL")
MUXCTRL(RCV100_muxctrl_reg80, 0x120F0140, "GPIO8_6", "RGMII0_RXER")
MUXCTRL(RCV100_muxctrl_reg81, 0x120F0144, "GPIO6_6", "EPHY0_CLK")
MUXCTRL(RCV100_muxctrl_reg82, 0x120F0148, "GPIO6_4", "EPHY0_RSTN")
MUXCTRL(RCV100_muxctrl_reg83, 0x120F014C, "GPIO10_0", "MDCK0")
MUXCTRL(RCV100_muxctrl_reg84, 0x120F0150, "GPIO10_1", "MDIO0")
MUXCTRL(RCV100_muxctrl_reg85, 0x120F0154, "GPIO10_2", "IR_IN")
MUXCTRL(RCV100_muxctrl_reg86, 0x120F0158, "SFC_MOSI_IO0", "GPIO11_0")
MUXCTRL(RCV100_muxctrl_reg87, 0x120F015C, "SFC_WP_IO2", "GPIO11_1")
MUXCTRL(RCV100_muxctrl_reg88, 0x120F0160, "SFC_MISO_IO1", "GPIO11_2")
MUXCTRL(RCV100_muxctrl_reg89, 0x120F0164, "GPIO13_0", "USB2_OVRCUR0")
MUXCTRL(RCV100_muxctrl_reg90, 0x120F0168, "GPIO13_1", "USB2_PWREN0")
MUXCTRL(RCV100_muxctrl_reg91, 0x120F016C, "GPIO13_2", "USB2_OVRCUR1")
MUXCTRL(RCV100_muxctrl_reg92, 0x120F0170, "GPIO13_3", "USB2_PWREN1")
MUXCTRL(RCV100_muxctrl_reg93, 0x120F0174, "GPIO13_4", "HDMI_HOTPLUG")
MUXCTRL(RCV100_muxctrl_reg95, 0x120F017C, "GPIO13_6", "HDMI_SDA")
MUXCTRL(RCV100_muxctrl_reg96, 0x120F0180, "GPIO13_7", "HDMI_SCL")
MUXCTRL(RCV100_muxctrl_reg97, 0x120F0184, "GPIO10_3", "SATA_LED_N0")
MUXCTRL(RCV100_muxctrl_reg98, 0x120F0188, "GPIO10_4", "SATA_LED_N1")

static const muxctrl_reg_t *RCV100regs[] = {
    &RCV100_muxctrl_reg0,  &RCV100_muxctrl_reg1,  &RCV100_muxctrl_reg2,
    &RCV100_muxctrl_reg3,  &RCV100_muxctrl_reg4,  &RCV100_muxctrl_reg5,
    &RCV100_muxctrl_reg6,  &RCV100_muxctrl_reg7,  &RCV100_muxctrl_reg8,
    &RCV100_muxctrl_reg9,  &RCV100_muxctrl_reg10, &RCV100_muxctrl_reg11,
    &RCV100_muxctrl_reg12, &RCV100_muxctrl_reg13, &RCV100_muxctrl_reg14,
    &RCV100_muxctrl_reg15, &RCV100_muxctrl_reg16, &RCV100_muxctrl_reg17,
    &RCV100_muxctrl_reg18, &RCV100_muxctrl_reg20, &RCV100_muxctrl_reg38,
    &RCV100_muxctrl_reg39, &RCV100_muxctrl_reg43, &RCV100_muxctrl_reg44,
    &RCV100_muxctrl_reg45, &RCV100_muxctrl_reg46, &RCV100_muxctrl_reg47,
    &RCV100_muxctrl_reg48, &RCV100_muxctrl_reg49, &RCV100_muxctrl_reg50,
    &RCV100_muxctrl_reg51, &RCV100_muxctrl_reg52, &RCV100_muxctrl_reg53,
    &RCV100_muxctrl_reg54, &RCV100_muxctrl_reg55, &RCV100_muxctrl_reg56,
    &RCV100_muxctrl_reg57, &RCV100_muxctrl_reg58, &RCV100_muxctrl_reg59,
    &RCV100_muxctrl_reg60, &RCV100_muxctrl_reg61, &RCV100_muxctrl_reg62,
    &RCV100_muxctrl_reg63, &RCV100_muxctrl_reg64, &RCV100_muxctrl_reg65,
    &RCV100_muxctrl_reg66, &RCV100_muxctrl_reg67, &RCV100_muxctrl_reg68,
    &RCV100_muxctrl_reg69, &RCV100_muxctrl_reg70, &RCV100_muxctrl_reg71,
    &RCV100_muxctrl_reg72, &RCV100_muxctrl_reg73, &RCV100_muxctrl_reg74,
    &RCV100_muxctrl_reg75, &RCV100_muxctrl_reg76, &RCV100_muxctrl_reg77,
    &RCV100_muxctrl_reg78, &RCV100_muxctrl_reg79, &RCV100_muxctrl_reg80,
    &RCV100_muxctrl_reg81, &RCV100_muxctrl_reg82, &RCV100_muxctrl_reg83,
    &RCV100_muxctrl_reg84, &RCV100_muxctrl_reg85, &RCV100_muxctrl_reg86,
    &RCV100_muxctrl_reg87, &RCV100_muxctrl_reg88, &RCV100_muxctrl_reg89,
    &RCV100_muxctrl_reg90, &RCV100_muxctrl_reg91, &RCV100_muxctrl_reg92,
    &RCV100_muxctrl_reg93, &RCV100_muxctrl_reg95, &RCV100_muxctrl_reg96,
    &RCV100_muxctrl_reg97, &RCV100_muxctrl_reg98, 0,
};

static int gpio_mux_by(const char *gpio_number, int func_num,
                       const char *set_func);

static const char *get_function(const char *const *func, unsigned val) {
    for (size_t i = 0; func[i]; i++) {
        if (i == val)
            return func[i] ? func[i] : "reserved";
    }

    return "reserved";
}

static void show_function(const char *const *func, unsigned val) {
    for (size_t i = 0; func[i]; i++) {
        if (i == val)
            printf(" [%s]", func[i] ? func[i] : "reserved");
        else
            printf(" %s", func[i] ? func[i] : "reserved");
    }
    puts("");
}

static const muxctrl_reg_t **regs_by_chip() {
    switch (chip_generation) {
    case HISI_V1:
        return CV100regs;
    case HISI_V2A:
        return AV100regs;
    case HISI_V2:
        if (IS_CHIP("3516CV200"))
            return CV200regs;
        else
            return EV20Xregs;
    case HISI_V3A:
        return AV200regs;
    case HISI_V3:
        return CV300regs;
    case HISI_V4A:
        if (IS_CHIP("3516CV500"))
            return CV500regs;
        else
            return DV300regs;
    case HISI_V4:
        if (IS_16EV200)
            return EV200regs;
        else if (IS_16EV300)
            return EV300regs;
        else if (IS_18EV300)
            return _8EV300regs;
        else if (IS_16DV200)
            return DV200regs;
        break;
    case HISI_3536C:
        return RCV100regs;
    case HISI_3536D:
        return DV100regs;
    }
    fprintf(stderr, "Platform is not supported\n");
    exit(EXIT_FAILURE);
}

static int dump_regs(bool script_mode) {
    const muxctrl_reg_t **regs = regs_by_chip();

    for (int reg_num = 0; regs[reg_num]; reg_num++) {
        uint32_t val;
        if (!mem_reg(regs[reg_num]->address, &val, OP_READ)) {
            printf("read reg %#x error\n", regs[reg_num]->address);
            continue;
        }

        if (script_mode) {
            printf("devmem %#x 32 %#x\n", regs[reg_num]->address, val);
            continue;
        }

        val &= 0xf;
        printf("muxctrl_reg%d %#x %#x", reg_num, regs[reg_num]->address, val);
        show_function(regs[reg_num]->funcs, val);
    }

    return EXIT_SUCCESS;
}

extern void print_usage();

int reginfo_cmd(int argc, char **argv) {
    const struct option long_options[] = {
        {"script", no_argument, NULL, 's'},
        {NULL, 0, NULL, 0},
    };
    bool script_mode = false;
    int res;
    int option_index;

    while ((res = getopt_long_only(argc, argv, "s", long_options,
                                   &option_index)) != -1) {
        switch (res) {
        case 's':
            script_mode = true;
            break;
        case '?':
            print_usage();
            return EXIT_FAILURE;
        }
    }

    getchipname();

    return dump_regs(script_mode);
}

static void print_bin(size_t data, size_t enabled) {
    for (int i = 7; i >= 0; i--) {
        if (!(enabled >> i & 1))
            printf("x");
        else if (data >> i & 1)
            printf("1");
        else
            printf("0");
    }
}

static void print_line(unsigned int cnt) {
    char buffer[cnt + 1];
    memset(buffer, '=', cnt);
    buffer[cnt] = '\0';
    printf("%s\n", buffer);
}

static bool get_chip_gpio_adress(size_t *GPIO_Base, size_t *GPIO_Offset,
                                 int *GPIO_Groups) {
    *GPIO_Offset = 0x10000;

    switch (chip_generation) {
    case HISI_V1:
        *GPIO_Base = 0x20140000;
        *GPIO_Groups = 12;
        break;
    case HISI_V2A:
        *GPIO_Base = 0x20140000;
        *GPIO_Groups = IS_CHIP("3516AV100") ? 17 : 15;
        break;
    case HISI_V2:
        *GPIO_Base = 0x20140000;
        *GPIO_Groups = 9;
        break;
    case HISI_V3A:
        *GPIO_Base = 0x12140000;
        *GPIO_Groups = 16;
        *GPIO_Offset = 0x1000;
        break;
    case HISI_V3:
        *GPIO_Base = 0x12140000;
        *GPIO_Groups = 9;
        *GPIO_Offset = 0x1000;
        break;
    case HISI_V4A:
        // AV300
        *GPIO_Base = 0x120D0000;
        *GPIO_Groups = 12;
        *GPIO_Offset = 0x1000;
        break;
    case HISI_V4:
        *GPIO_Base = 0x120B0000;
        *GPIO_Groups = IS_16EV300 || IS_16DV200 ? 10 : 9;
        *GPIO_Offset = 0x1000;
        break;
    case HISI_3536C:
        *GPIO_Base = 0x12150000;
        *GPIO_Groups = 14;
        break;
    case HISI_3536D:
        *GPIO_Base = 0x12150000;
        *GPIO_Groups = 6;
        break;
    default:
        return false;
    }
    return true;
}

static int gpio_manipulate(char **argv, bool set_op) {
    int GPIO_Groups = 0;
    size_t GPIO_Base = 0;
    size_t GPIO_Offset = 0;

    getchipname();
    if (!get_chip_gpio_adress(&GPIO_Base, &GPIO_Offset, &GPIO_Groups)) {
        fprintf(stderr, "Chip is not supported\n");
        return EXIT_FAILURE;
    }

    const char *gpio_num = argv[1];
    gpio_mux_by(gpio_num, -1, NULL);

    int group, num;
    if (sscanf(gpio_num, "%d_%d", &group, &num) != 2) {
        num = strtoul(gpio_num, NULL, 10);
        group = num / 8;
        num %= 8;
    }
    if (group > GPIO_Groups || num > 7)
        return EXIT_FAILURE;

    size_t mask = 1 << (2 + num);
    uint32_t val, address = GPIO_Base + (group * GPIO_Offset) + mask;

    if (set_op) {
        unsigned val = strtoul(argv[2], NULL, 10);
        if (val > 1)
            return EXIT_FAILURE;

        size_t daddress = GPIO_Base + (group * GPIO_Offset) + 0x400;
        uint32_t direct;
        if (!mem_reg(daddress, &direct, OP_READ)) {
            fprintf(stderr, "read reg %#x error\n", address);
            return EXIT_FAILURE;
        }
        if (((direct >> num) & 1U) == 0) {
            // If current state is input, set bit it make it output
            direct |= 1UL << num;
            if (!mem_reg(daddress, &direct, OP_WRITE)) {
                fprintf(stderr, "write reg %#x error\n", address);
                return EXIT_FAILURE;
            }
        }

        uint32_t cmd = val << num;
        if (!mem_reg(address, &cmd, OP_WRITE)) {
            printf("write reg %#x error\n", address);
            return EXIT_FAILURE;
        }
    } else {
        if (!mem_reg(address, &val, OP_READ)) {
            printf("read reg %#x error\n", address);
            return EXIT_FAILURE;
        }
        printf("%d\n", val ? 1 : 0);
    }

    return EXIT_SUCCESS;
}

static int gpio_get_cmd(int argc, char **argv) {
    if (argc != 2) {
        printf("Usage: ipctool gpio %s <gpio number>%s\n%s", "get", "",
               "where: <gpio number> either number in 5_6 or 46 format\n");
        return EXIT_FAILURE;
    }

    return gpio_manipulate(argv, false);
}

static int gpio_set_cmd(int argc, char **argv) {
    if (argc != 3) {
        printf("Usage: ipctool gpio %s <gpio number>%s\n%s", "set", " <value>",
               "where: <gpio number> either number in 5_6 or 46 format\n");
        return EXIT_FAILURE;
    }

    return gpio_manipulate(argv, true);
}

static const char *num2gpio_groupnum(const char *gpio_name, char cgpio[64]) {
    if (strchr(gpio_name, '_') != NULL)
        return gpio_name;

    unsigned long plain_num = strtoul(gpio_name, NULL, 10);
    int group = plain_num / 8;
    int num = plain_num % 8;
    snprintf(cgpio, 64, "%d_%d", group, num);
    return cgpio;
}

static int find_pinfunc(const char *const *func, const char *name) {
    for (int i = 0; func[i]; i++) {
        if (!strcmp(func[i], name))
            return i;
    }

    return -1;
}

static int gpio_mux_by(const char *gpio_number, int func_num,
                       const char *set_func) {
    const char *gpio_grnum = num2gpio_groupnum(gpio_number, (char[64]){0});
    if (gpio_grnum == NULL)
        return EXIT_FAILURE;

    getchipname();
    const muxctrl_reg_t **regs = regs_by_chip();

    for (int reg_num = 0; regs[reg_num]; reg_num++) {
        const char *const *func = regs[reg_num]->funcs;
        for (int i = 0; func[i]; i++) {
            if ((!strncmp("GPIO", func[i], 4)) &&
                (!strcmp(func[i] + 4, gpio_grnum))) {

                uint32_t val;
                if (!mem_reg(regs[reg_num]->address, &val, OP_READ)) {
                    printf("read reg %#x error\n", regs[reg_num]->address);
                    return EXIT_FAILURE;
                }

                int new_func = func_num;
                if (new_func == -1 && set_func != NULL)
                    new_func = find_pinfunc(func, set_func);

                if (new_func == -1)
                    new_func = i;
                val = val & 0xfff0 | new_func;
                if (!mem_reg(regs[reg_num]->address, &val, OP_WRITE)) {
                    printf("write reg %#x error\n", regs[reg_num]->address);
                    return EXIT_FAILURE;
                }

                return EXIT_SUCCESS;
            }
        }
    }

    fprintf(stderr, "GPIO %s is not found\n", gpio_grnum);
    return EXIT_FAILURE;
}

static int gpio_mux_cmd(int argc, char **argv) {
    if (argc < 2 || argc > 3) {
        printf("Usage: ipctool gpio %s <gpio number>%s\n%s", "mux",
               " [function name or number]",
               "where: <gpio number> either number in 5_6 or 46 format\n");
        return EXIT_FAILURE;
    }

    const char *set_func = NULL;
    int func_num = -1;
    if (argc == 3) {
        set_func = argv[2];
        if (isdigit(set_func[0]))
            func_num = strtoul(set_func, NULL, 10);
    }

    return gpio_mux_by(argv[1], func_num, set_func);
}

static void fill_enabled_gpios(size_t *enabled, size_t GPIO_Groups) {
    const muxctrl_reg_t **regs = regs_by_chip();

    memset(enabled, 0, sizeof(size_t) * GPIO_Groups);
    for (int reg_num = 0; regs[reg_num]; reg_num++) {
        const char *const *func = regs[reg_num]->funcs;
        for (size_t i = 0; func[i]; i++) {
            if (!strncmp("GPIO", func[i], 4)) {
                uint32_t val;
                if (!mem_reg(regs[reg_num]->address, &val, OP_READ)) {
                    printf("read reg %#x error\n", regs[reg_num]->address);
                    continue;
                }

                if ((val & 0xf) == i) {
                    int group, num;
                    if (sscanf(func[i] + 4, "%d_%d", &group, &num) != 2)
                        assert("Parsing error");
                    assert(group <= GPIO_Groups);
                    enabled[group] |= 1 << num;
                }
                break;
            }
        }
    }
}

char *gpio_possible_ircut(char *outbuf, size_t outlen) {
    int GPIO_Groups = 0;
    size_t GPIO_Base = 0;
    size_t GPIO_Offset = 0;

    *outbuf = 0;
    if (!get_chip_gpio_adress(&GPIO_Base, &GPIO_Offset, &GPIO_Groups))
        return NULL;

    size_t enabled[GPIO_Groups];
    fill_enabled_gpios(enabled, GPIO_Groups);

    char *ptr = outbuf;
    for (int group = 0; group < GPIO_Groups; group++) {
        size_t mask = enabled[group] << 2;
        size_t address = GPIO_Base + (group * GPIO_Offset) + mask;
        uint32_t value;
        if (!mem_reg(address, &value, OP_READ)) {
            fprintf(stderr, "Error at %#zx\n", address);
            return NULL;
        }
        address = GPIO_Base + (group * GPIO_Offset) + 0x400;
        uint32_t direct;
        if (!mem_reg(address, &direct, OP_READ)) {
            fprintf(stderr, "Error at %#zx\n", address);
            return NULL;
        }

        for (int i = 0; i < 8; i++) {
            uint8_t bit_mask = 1 << i;
            if (enabled[group] >> i & 1)
                if ((direct & bit_mask) && ((value & bit_mask) == 0)) {
                    int nlen = snprintf(ptr, outlen, ",%d", group * 8 + i);
                    outlen -= nlen;
                    ptr += nlen;
                }
        }
    }

    if (strlen(outbuf) > 0)
        return outbuf + 1;
    else
        return NULL;
}

static int gpio_scan_cmd() {
    int GPIO_Groups = 0;
    size_t GPIO_Base = 0;
    size_t GPIO_Offset = 0;

    getchipname();
    if (!get_chip_gpio_adress(&GPIO_Base, &GPIO_Offset, &GPIO_Groups))
        return EXIT_FAILURE;

    size_t state[GPIO_Groups];
    size_t enabled[GPIO_Groups];
    fill_enabled_gpios(enabled, GPIO_Groups);

    for (int group = 0; group < GPIO_Groups; group++) {
        size_t mask = enabled[group] << 2;
        size_t address = GPIO_Base + (group * GPIO_Offset) + mask;
        uint32_t value;
        if (!mem_reg(address, &value, OP_READ)) {
            fprintf(stderr, "Error at %#zx\n", address);
            return EXIT_FAILURE;
        }
        state[group] = value;
        printf("Gr:%2d, Addr:0x%08zX, Data:0x%02X = 0b", group, address, value);
        print_bin(value, enabled[group]);
        address = GPIO_Base + (group * GPIO_Offset) + 0x400;
        uint32_t direct;
        if (!mem_reg(address, &direct, OP_READ)) {
            fprintf(stderr, "Error at %#zx\n", address);
            return EXIT_FAILURE;
        }
        printf(", Addr:0x%08zX, Dir:0x%02X = 0b", address, direct);
        print_bin(direct, enabled[group]);
        printf("\n");
    }

    print_line(86);
    printf("Waiting for while something changes...\n");
    while (1) {
        for (int group = 0; group < GPIO_Groups; group++) {
            size_t mask = enabled[group] << 2;
            size_t address = GPIO_Base + (group * GPIO_Offset) + mask;
            uint32_t value;
            if (!mem_reg(address, &value, OP_READ)) {
                fprintf(stderr, "Error at %#zx\n", address);
                break;
            }
            if (state[group] != value) {
                bool HeaderByte = false;
                for (int bit = 7; bit >= 0; bit--) {
                    int old_bit = (state[group] >> bit) & 1;
                    int new_bit = (value >> bit) & 1;
                    if (old_bit != new_bit) {
                        if (HeaderByte == false) {
                            print_line(86);
                            printf("Gr:%d, Addr:0x%08zX, Data:0x%02zX = 0b",
                                   group, address, state[group]);
                            print_bin(state[group], enabled[group]);
                            printf(" --> 0x%02X = 0b", value);
                            print_bin(value, enabled[group]);
                            printf("\n");
                            HeaderByte = true;
                        }
                        address = GPIO_Base + (group * GPIO_Offset) + 0x400;
                        uint32_t direct;
                        if (!mem_reg(address, &direct, OP_READ)) {
                            fprintf(stderr, "Error at %#zx\n", address);
                            break;
                        }
                        direct = (direct >> bit) & 1;
                        address = GPIO_Base + (group * GPIO_Offset) +
                                  (1 << (bit + 2));
                        int mask = value & 1 << bit;
                        printf("Mask: \"devmem 0x%08zX 32 0x%02X\", "
                               "GPIO%d_%d, GPIO%d, "
                               "Dir:%s, Level:%d\n",
                               address, mask, group, bit, (group * 8) + bit,
                               direct ? "Output" : "Input", new_bit);
                    }
                }
                state[group] = value;
            }
        }
        usleep(100000);
    }

    return EXIT_SUCCESS;
}

int gpio_cmd(int argc, char **argv) {
    if (argc > 1) {
        if (!strcmp(argv[1], "scan"))
            return gpio_scan_cmd();
        else if (!strcmp(argv[1], "mux"))
            return gpio_mux_cmd(argc - 1, argv + 1);
        else if (!strcmp(argv[1], "get"))
            return gpio_get_cmd(argc - 1, argv + 1);
        else if (!strcmp(argv[1], "set"))
            return gpio_set_cmd(argc - 1, argv + 1);
    }

    printf("Usage: ipctool gpio <command>\n");
    return EXIT_FAILURE;
}