Optimize CRC calculation for RISC-V64 architecture · Pull Request !12 · src-openEuler/isa-l

Optimize CRC calculation for the RISC-V64 architecture by replacing
 time-consuming vredxor.vv instructions with better performance
 combination of vslidexx.vi and vxor.vv instructions. Dependencies on
 the Zvbb extension have been removed.

Testing
 The verification method involves
 running autogen.sh and configure to generate the Makefile, followed by
 executing the make checks command. The verification results below were
 obtained on a RISC-V64 OpenEuler 24.03 virtual machine on QEMU 9.0.1

All tests successful.
 make --no-print-directory check-TESTS
 PASS: raid/pq_gen_test
 PASS: crc/crc16_t10dif_test
 PASS: crc/crc16_t10dif_copy_test
 PASS: raid/xor_gen_test
 PASS: crc/crc64_funcs_test
 PASS: crc/crc32_funcs_test
 PASS: igzip/igzip_wrapper_hdr_test
 PASS: igzip/checksum32_funcs_test
 PASS: erasure_code/gf_inverse_test
 PASS: erasure_code/gf_vect_mul_test
 PASS: raid/xor_check_test
 PASS: raid/pq_check_test
 PASS: igzip/igzip_rand_test
 PASS: mem/mem_zero_detect_test
 PASS: erasure_code/erasure_code_test
 PASS: erasure_code/erasure_code_update_test
 ============================================================================
 Testsuite summary for libisal 2.30.0
 ============================================================================
 # TOTAL: 16
 # PASS:  16
 # SKIP:  0
 # XFAIL: 0
 # FAIL:  0
 # XPASS: 0
 # ERROR: 0
 ============================================================================

Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn>

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