[sync] PR-178: Enable unaligned memory accesses for RISC-V, got performance improvements testing siphash separately · Pull Request !188 · src-openEuler/redis

### 1. Origin pull request:
https://gitee.com/src-openeuler/redis/pulls/178

### 2. Original pull request related issue(s):
https://gitee.com/src-openeuler/redis/issues/ICZVP3

### 3. Original pull request related commit(s):
| Sha | Datetime | Message |
|---|---|---|
|[a0a4b96d](https://gitee.com/src-openeuler/redis/commits/a0a4b96dbc11a0e98cebe93e97a0772f44472069)|2025-09-25 11:04:56 +0800 CST|While reviewing the Redis code, we discovered that optimizations for unaligned memory accesses are not enabled on RISC-V. After testing siphash separately, we found some performance improvements in this area and hope to add them. The zicclsm extension, which includes unaligned memory accesses, is required on RISC-V, as specified in the RVA20U64 specification. GCC also provides the macro zicclsm to detect the zicclsm extension. Supported versions: GCC 14.1.0 and above Test data Test Configuration Test Iterations: 10,000,000 hashes per run Test Runs: 10 consecutive runs Improvement 6482733.40 --> 10732524.90 (+65.5%) Disable UNALIGNED_LE_CPU Running performance test (10 runs)... Run 1: 6491958.63 hashes/sec Run 2: 6487366.83 hashes/sec Run 3: 6481576.94 hashes/sec Run 4: 6484129.18 hashes/sec Run 5: 6486451.34 hashes/sec Run 6: 6476159.22 hashes/sec Run 7: 6479075.32 hashes/sec Run 8: 6476821.02 hashes/sec Run 9: 6482822.05 hashes/sec Run 10: 6480973.47 hashes/sec Average performance: 6482733.40 hashes/sec Enable UNALIGNED_LE_CPU Running performance test (10 runs)... Run 1: 10724141.20 hashes/sec Run 2: 10736134.67 hashes/sec Run 3: 10733149.45 hashes/sec Run 4: 10732901.09 hashes/sec Run 5: 10731710.56 hashes/sec Run 6: 10734029.89 hashes/sec Run 7: 10733342.07 hashes/sec Run 8: 10732782.90 hashes/sec Run 9: 10733797.15 hashes/sec Run 10: 10733260.05 hashes/sec Average performance: 10732524.90 hashes/sec Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn> |

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