• 1
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tomhuangsrc / DisplayPort_Verilog

A Verilog implementation of DisplayPort protocol for FPGAs

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• 0

tomhuangsrc / Distributed_Recommendation_Inference_on_FPGA_Clusters

• 1
• 0
• 0

tomhuangsrc / HW_LCAI-TIHU

LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.

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tomhuangsrc / hls4ml

Machine learning on FPGAs using HLS

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tomhuangsrc / fpga-trading-systems

Complete end-to-end FPGA trading system: hardware acceleration (<5μs latency), kernel bypass (AF_XDP, DPDK), automated market maker, FIX 4.2 execution engine. 35 projects from Ethernet PHY to multi-platform apps. Real NASDAQ ITCH validation (563K+ samples). Production-grade low-latency architecture. LLM-Inference

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tomhuangsrc / YuQuan

• 1
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tomhuangsrc / MemoryTools

• 1
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tomhuangsrc / MCSim

• 1
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tomhuangsrc / ztachip

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

• 1
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tomhuangsrc / daily-arXiv-ai-enhanced

Automatically crawl arXiv papers daily and summarize them using AI. Illustrating them using GitHub Pages.

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tomhuangsrc / agilex7-ed-pcie-rp

Altera Agilex 7 PCIe Root Port System Example Design

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• 0

tomhuangsrc / UCIe-Controller

Complete UCIe v2.0 Controller RTL Implementation with Revolutionary 128 Gbps PAM4 Signaling - Architecture Design Complete, Ready for RTL Development

• 1
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• 0

tomhuangsrc / AFXSATA

FPGA-based SATA-DMA Host Controller

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• 2

tomhuangsrc / fpga-network-stack forked from wyh / fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

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• 0
• 1

tomhuangsrc / RSIC-V hardware forked from 挪更你港 / RSIC-V hardware

RSIC-V开源硬件代码

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• 45

tomhuangsrc / openTSN forked from opentsn / openTSN

开源的时间敏感网络(TSN)环境