import os, sys, argparse

class VerilogBuilder:
    def __init__(self, output_path="output", output="wave") -> None:
        self.m_output_path = output_path
        self.m_output = output

    def __mk_output_dir(self):
        if(not os.path.isdir(self.m_output_path)):
            os.mkdir(self.m_output_path)

    def build(self, srcs: list):
        self.__mk_output_dir()
        src_str = " ".join(srcs)
        os.system(f"iverilog -o {self.m_output_path}/{self.m_output} {src_str}")
        os.system(f"cd {self.m_output_path} && vvp -n {self.m_output} -lxt2")

    def show_wave(self):
        os.system(f"cd {self.m_output_path} && gtkwave {self.m_output}.vcd")


if __name__ == "__main__":
    parser = argparse.ArgumentParser([])
    parser.add_argument("-p","--path", default="led_demo", type=str, help="verilog srcs dir")
    args = parser.parse_args()
    if(not args.path.endswith('/')):
        args.path = args.path + '/'
    vbuilder = VerilogBuilder()
    files = os.listdir(args.path)
    print(files)
    srcs=[]
    for f in files:
        f = args.path+f
        if(os.path.isfile(f) and f.endswith(".v")):
            srcs.append(f)
    
    print(srcs)
    vbuilder.build(srcs)
    vbuilder.show_wave()