source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

# 设置基本环境
if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME HC32F448
}

if { [info exists ENDIAN] } {
   set _ENDIAN $ENDIAN
} else {
   set _ENDIAN little
}

if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   # set _CPUTAPID 0x2ba01477
   # set _CPUTAPID 0x4ba00477
   set _CPUTAPID 0x2ba01477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# 设置flash名
set _FLASHNAME $_CHIPNAME.bank1
# flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME

proc test-test { } {
    echo 12345
}

adapter_nsrst_delay 100

reset_config srst_nogate

if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    debug_level 2
    cortex_m reset_config sysresetreq
    # cortex_m reset_config vectreset
}

$_TARGETNAME configure -event examine-end {
	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
   # echo 2222222
	# mmw 0xE0042004 0x00000307 0
}

$_TARGETNAME configure -event trace-config {
	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
	# change this value accordingly to configure trace pins
	# assignment
   # echo 333333
	# mmw 0xE0042004 0x00000020 0
}

# mcu不支持软断点. 这时需要openocd启动时设置
#     软断点转为硬件断点, 实际参数有 hard|soft|disable
#     详细可以找相关文档 Server-Configuration.html#gdbbreakpointoverride
gdb_breakpoint_override hard