`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2018/03/24 13:46:29
// Design Name: 
// Module Name: DIV
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module DIV(
    input RST,
    input CLK_IN,
    output CLK_OUT,
    input [7:0] DIV_NUM
    );
    
    reg clkout_reg = 1'b0;
    reg[7:0] div_cnt = 8'd0;
    
    assign CLK_OUT = clkout_reg;
    
    always@(posedge CLK_IN or negedge RST)
    begin
    if ( !RST )
    begin
        div_cnt <= 8'd0;
        clkout_reg <= 1'b0;     
    end
    else
    begin
        if ( div_cnt == DIV_NUM - 8'd1 )
        begin
            div_cnt <= 8'd0;
            clkout_reg <= ~clkout_reg;
        end
        else
        begin
            div_cnt <= div_cnt + 8'd1;
            clkout_reg <= clkout_reg;
        end
    
    end
    
    
    end
endmodule