`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2018/02/03 18:49:12
// Design Name: 
// Module Name: SPIV01
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module SPIV01(
    input RST,
    input SCK,
    input MOSI,
    input CS,
    output [15:0] DATA,
    output [7:0] LED,
    output data_update
    );

reg [15:0] data_reg = 16'd0;
reg [15:0] rece_reg = 16'd0;
reg update_Reg = 1'b1;


  
assign DATA = data_reg;
assign LED[7:0] = data_reg[15:8];
assign data_update = update_Reg;

reg [7:0] pluse_cnt = 8'd0;
reg cnt_rst = 1'b1;
reg cnt_rst_pre = 1'b1;
always@( posedge CS )
begin
    cnt_rst <= ~cnt_rst;
end

always@( posedge SCK )
begin
    if ( !RST || CS )
    begin
        rece_reg <= 16'd0;
        pluse_cnt <= 8'd0;
        update_Reg <= 1'b1;
    end
    else
    begin
        rece_reg[16'd15 -  pluse_cnt ] <= MOSI;
        if ( pluse_cnt == 16'd0 )
        begin                
            pluse_cnt <= pluse_cnt + 8'd1;
            update_Reg <= 1'b1; 
            data_reg <= rece_reg;   
        end
        else if ( pluse_cnt == 16'd1 )
        begin
            pluse_cnt <= pluse_cnt + 8'd1;
            update_Reg <= 1'b0; //给一个下跳沿刷新buff数据
            data_reg <= data_reg;
        end
        else if ( pluse_cnt == 8'd15 )
        begin
            pluse_cnt <= 8'd0;
            update_Reg <= 1'b1;
            data_reg <= data_reg;
        end
        else
        begin
            pluse_cnt <= pluse_cnt + 8'd1;
            update_Reg <= 1'b1;
            data_reg <= data_reg;
        end
        
        //做一个对齐保护
        if ( cnt_rst_pre != cnt_rst )
        begin
            cnt_rst_pre <= cnt_rst;
            pluse_cnt <= 8'd1;
        end
    end
end
       
    
endmodule