`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2018/02/04 14:29:15
// Design Name: 
// Module Name: pingpongv01
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pingpongv01(
    input CLK, //系统时钟
    input CS,//buff对齐信号
    input [15:0] SPI_IN,  //从SPI获得8位数据
    input I2S_LRCK,   //从I2S获得左右声道信息
    input REC_FNS,  //SPI每传一个byte
    input RST,
    output [15:0] I2S_OUT,//给I2S传16位数据
    output [7:0] LED,
    output SPI_REFLASH//允许SPI刷新
    );
    
    reg buff_sw = 1'b0;
    reg buff_sw_pre = 1'b0;
    reg reflash_reg = 1'b0;
    reg [7:0] buff_A[0:2303];
    reg [7:0] buff_B[0:2303];
    reg [15:0] i2sout_reg = 16'b0;
    reg [15:0] rec_cnt = 16'd0;
    reg [15:0] snd_cnt = 16'd0;
    
    reg init_reg = 1'b0;//初始化完成标志
    
    assign I2S_OUT = i2sout_reg;
    
    assign SPI_REFLASH = reflash_reg;
    assign LED = i2sout_reg[15:8];
    
    always@( negedge REC_FNS or negedge RST or posedge CS)
    begin
        if ( !RST )
        begin
            rec_cnt <= 16'd0;
            buff_sw_pre <= 1'b0;
        end
        else if ( CS )
        begin
            rec_cnt <= 16'd0;
            buff_sw_pre <= buff_sw_pre;
        end
        else if ( buff_sw_pre != buff_sw )//buff有切换,此时是0，下次是1
        begin
            buff_sw_pre <= buff_sw;
            rec_cnt <= 16'd1;
            if ( buff_sw == 1'b0 && init_reg ) //填B发A //没初始化完成不填B，只填A
            begin
                buff_A[0] <= buff_A[0];
                buff_B[0] <= SPI_IN[15:8];
            end
            else//填A发B
            begin
                buff_A[0] <= SPI_IN[15:8];
                buff_B[0] <= buff_B[0];
            end         
        end
        else 
        begin
            buff_sw_pre <= buff_sw_pre;
            if ( rec_cnt == 16'd2303 )
            begin
                rec_cnt <= rec_cnt;
                init_reg <= 1'b1; //初始化完成，I2S可以传送
            end
            else
            begin
                rec_cnt <= rec_cnt + 16'd1;
            end
            
            if ( buff_sw == 1'b0 && init_reg ) //填B发A //没初始化完成不填B，只填A
            begin
                buff_A[rec_cnt] <= buff_A[rec_cnt];
                buff_B[rec_cnt] <= SPI_IN[15:8];
            end
            else//填A发B
            begin
                buff_A[rec_cnt] <= SPI_IN[15:8];
                buff_B[rec_cnt] <= buff_B[rec_cnt];
            end
        end
    end
   
    reg PRE_I2S_LRCK = 1'b0;
    
    //从BUFF送数据到I2S
    always@( posedge CLK or negedge RST )//88.2khz
    begin
        if( !RST || !init_reg )//初始化没有完成，不释放I2S
        begin
            snd_cnt <= 16'd0;
        
            i2sout_reg <= 16'b0;

            PRE_I2S_LRCK <= 1'b0;
            
            buff_sw <= 1'b0; //切buff
            reflash_reg <= 1;
        end
        
        else if ( PRE_I2S_LRCK == I2S_LRCK )
        begin
             PRE_I2S_LRCK <=  PRE_I2S_LRCK;
             i2sout_reg <= i2sout_reg;
        end
        
        else
        begin
            PRE_I2S_LRCK <= I2S_LRCK;  
                     
            if ( buff_sw == 1'b0 )//填B发A
            begin
                i2sout_reg[15:8] <= buff_A[snd_cnt];
            end
            else//填A发B
            begin
                i2sout_reg[15:8] <= buff_B[snd_cnt];
            end
        /////////////////////////////////////////////////////////////////    
            if ( snd_cnt == 16'd2303 )//发送完毕
            begin
                snd_cnt <= 16'd0;
                buff_sw <= ~buff_sw;//切换buff
                reflash_reg <= reflash_reg;
            end           
            else if ( snd_cnt == 16'd0 )
            begin
                snd_cnt <= snd_cnt + 16'd1;
                buff_sw <= buff_sw;
                reflash_reg <= 1'b0; // 要求SPI开始发送，填满空buff,下降沿 
            end
            
            else
            begin
                snd_cnt <= snd_cnt + 16'd1;
                buff_sw <= buff_sw;
                reflash_reg <= 1'b1;//复位
            end                      
        end
    end
    
    
endmodule