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shxu/verilog-pcie forked from funzero/verilog-pcie

Verilog PCI express components

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shxu/verilog-wishbone forked from funzero/verilog-wishbone

Verilog wishbone components

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shxu/sdio_controller_verilog forked from david6chen/sdio_controller_verilog

Controller SDIo host compatible with wishbone I/F {verilog}

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shxu/DisplayPort_Verilog forked from bingweiyang/DisplayPort_Verilog

A Verilog implementation of DisplayPort protocol for FPGAs

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shxu/uvm_axi-1 forked from 张文明/uvm_axi-1

uvm_axi is a uvm package for modeling and verifying AXI protocol

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shxu/axi-uvm forked from 张文明/axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

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shxu/uvm_axi forked from 张文明/uvm_axi

uvm AXI BFM(bus functional model)

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shxu/axi forked from dong/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

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shxu/axi-pulp forked from ic-starter/axi-pulp

AXI library from pulp-platform

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shxu/AMBA_AXI_AHB_APB forked from openfpga/AMBA_AXI_AHB_APB

github from https://github.com/adki/AMBA_AXI_AHB_APB

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shxu/verilog-axis forked from funzero/verilog-axis

Verilog AXI stream components for FPGA implementation

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shxu/verilog-axi forked from sspg/verilog-axi

clone的https://github.com/alexforencich/verilog-axi

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shxu/verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

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shxu/wujian100_open

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shxu/gitignore

A collection of useful .gitignore templates