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FiberCOMM/PSTR17R5B

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top_scck.rpt 1.90 KB
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FiberCOMM 提交于 2020-10-21 15:48 . 1.增益控制改为DS3502芯片
# Synospys Constraint Checker(syntax only), version maprc, Build 1495R, built Mar 1 2013
# Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
# Written on Sun Jun 21 19:46:44 2020
##### DESIGN INFO #######################################################
Top View: "top"
Constraint File(s): "F:\PSTR17R5B\top.sdc"
#Run constraint checker to find more issues with constraints.
#########################################################################
No issues found in constraint syntax.
Clock Summary
**************
Start Requested Requested Clock Clock
Clock Frequency Period Type Group
-----------------------------------------------------------------------------------------------------------------------------
System 1.0 MHz 1000.000 system system_clkgroup
top|clk 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
myicon|U0/U_ICON/I_YES_BSCAN_U_BS/iDRCK_LOCAL_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_1
myicon|U0/iUPDATE_OUT_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_2
top|clk_2 1.0 MHz 1000.000 inferred Inferred_clkgroup_3
=============================================================================================================================
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