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KINGE / zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

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KINGE / PlotNeuralNet

Latex code for making neural networks diagrams

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KINGE / draw_convnet

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KINGE / BinaryNet

Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1

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KINGE / XJTU-Tripler

This repository is the backup of XJTU-Tripler project, participating dac19 system design contest

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KINGE / tensorpack

A Neural Net Training Interface on TensorFlow, with focus on speed + flexibility

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KINGE / FPGA-Based-RNN-Accelerator-Using-Vivado-HLS

This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code into Hardware Description Languages (HDL).

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KINGE / FPGA-ZynqNet

FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS

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KINGE / CF10ResNet20TWNHLSPrj

The resnet20 cnn inference accelerator on cifar10 net about twn net with hls tool

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KINGE / DiracDeltaNet

PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs

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KINGE / MTCNN_with_HLS_On_FPGA

MTCNN with convolution reprogramed in c

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KINGE / hls_cnn_accelerator

A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.

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KINGE / finn-hlslib

Vivado HLS library for FINN

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KINGE / shufflenetv2_hls

A FPGA-based Accelerator for Shufflenetv2 implemented on Xillinx Zynq-7000 SoC

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KINGE / chisel-examples

Chisel examples and code snippets

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KINGE / CNN-On-FPGA

FPGA

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KINGE / chisel3

Chisel 3: A Modern Hardware Design Language

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KINGE / chisel-lab

Lab exercises for Chisel in the digital electronics 2 course at DTU

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KINGE / chisel-book

Digital Design with Chisel

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KINGE / chisel-template

A template project for beginning new Chisel work