Watch hfutlichao/pulpino forked from Gitee 极速下载/pulpino

PULPino是一个开源的微型控制系统,基于一个小32位RISC-V核心，由瑞士苏黎世联邦理工学院开发

Watch hfutlichao/lenet5-accelerator forked from KINGE/lenet5-accelerator

FPGA and GPU acceleration of LeNet5

Watch hfutlichao/verilog_notepadpp forked from cracy3m/verilog_notepadpp

notepad++ 编写Verilog相关设置

Watch hfutlichao/8-bits-RISC-CPU-Verilog forked from ynxing/8-bits-RISC-CPU-Verilog

Watch hfutlichao/SequenceMatchGenerator forked from misaka10418/SequenceMatchGenerator

使用python自动生成能够检测任意序列的Verilog模块

Watch hfutlichao/basic_verilog forked from zyq-77/basic_verilog

verilog的一些基本模块，避免重复造轮子

Watch hfutlichao/tinyriscv forked from liangkangnan/tinyriscv

一个从零开始写的极简、非常易懂的RISC-V处理器核。

Watch hfutlichao/kali-linux-web-pentest-cookbook-zh forked from 布客飞龙/kali-linux-web-pentest-cookbook-zh

[译] Kali Linux Web 渗透测试秘籍 中文版

Watch hfutlichao/memristor_simulations

Simulations using Brian for memristor-based neural networks using STDP learning

Watch hfutlichao/vlsi_memristor_compact_model

Physical memristor/RRAM/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship.