• 1
• 0
• 0

ilo5u / vexriscvgds

• 1
• 0
• 0

ilo5u / SpinalHDL

Scala based HDL

• 1
• 0
• 0

ilo5u / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

• 1
• 0
• 26

ilo5u / riscv-gcc forked from Gitee 极速下载 / riscv-gcc

• 1
• 0
• 5

ilo5u / riscv-newlib forked from Gitee 极速下载 / riscv-newlib

• 1
• 0
• 0

ilo5u / riscv-glibc

RISC-V port of GNU's libc

• 1
• 0
• 0

ilo5u / riscv-dejagnu

DejaGnu RISC-V port

• 1
• 0
• 0

ilo5u / riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

• 1
• 0
• 0

ilo5u / riscv-pk

RISC-V Proxy Kernel

• 1
• 0
• 0

ilo5u / riscv-tools

RISC-V Tools (ISA Simulator and Tests)

• 1
• 0
• 0

ilo5u / llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

• 1
• 0
• 0

ilo5u / brew

🍺 The missing package manager for macOS (or Linux)

• 1
• 0
• 0

ilo5u / riscv-openocd

Fork of OpenOCD that has RISC-V support

• 1
• 0
• 0

ilo5u / riscv-opcodes

RISC-V Opcodes

• 1
• 0
• 0

ilo5u / riscv-tests

• 1
• 0
• 0

ilo5u / riscv-isa-sim

Spike, a RISC-V ISA Simulator

• 1
• 0
• 0

ilo5u / krb5

mirror of MIT krb5 repository

• 1
• 0
• 0

ilo5u / nvdla-workload

Base NVDLA Workload for FireMarshal

• 1
• 0
• 0

ilo5u / cva6-wrapper

Wrapper for ETH Ariane Core

• 1
• 0
• 0

ilo5u / sifive-blocks

Common RTL blocks used in SiFive's projects