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justin371/my_vimrc

:dragon_face:Jude's vimrc for DV work(fine tuning for SV/UVM)

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justin371/axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

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• 1
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justin371/combinator-uvm

UVM Testbench For SystemVerilog Combinator Implementation

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• 1
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justin371/uvm_debug

UVM interactive debug library

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• 5
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justin371/USTC-RVSoC

基于 FPGA 的 RISC-V CPU + SoC

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• 1
• 0

justin371/uvm-tutorial-for-candy-lovers

Source code repo for UVM Tutorial for Candy Lovers

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• 1
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justin371/SystemVerilogReference

training labs and examples

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• 0
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justin371/UVMReference

Reference examples and short projects using UVM Methodology

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justin371/i2c_wb_sv_uvm

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• 0
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justin371/use_vim_as_ide

use vim as IDE

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justin371/Verification

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justin371/YASA

:snail:Yet Another Simulation Architecture

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justin371/AHB2

AMBA AHB 2.0 VIP in SystemVerilog UVM

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• 0
• 0

justin371/awesome-c-cn

C 资源大全中文版，包括了：构建系统、编译器、数据库、加密、初中高的教程/指南、书籍、库等。

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justin371/awesome-dv

Awesome ASIC design verification

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justin371/uvm-python

UVM 1.2 port to Python

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• 0

justin371/tvip-axi

AMBA AXI VIP

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justin371/UVM_UART_Example

An UVM example of UART

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• 0
• 0

justin371/CPlusPlusThings

C++那些事

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• 9
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justin371/yuu_ahb

UVM AHB VIP