This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Refer to: https://drive.google.com/drive/folders/1fyUhUR0x1b1HQYjlndnEte-GhuKZ9sJ6
-> VerilogA References:
https://github.com/muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system/tree/master/%5B1%5D%20PLL%20System%20Level%20(VerilogAMS%20-%20Matlab)/VerilogA%20References%20(for%20PLLs)
-> PLL Design References:
https://github.com/muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system/tree/master/%5B2%5D%20PLL%20Circuit%20Design/References
My project on google drive:
https://drive.google.com/drive/folders/1TUYCLbdZC5S4dQVAxZmoUjMQPiLFntPe
EE230 Lecture Notes:
https://drive.google.com/open?id=1WcP2svOrAle0cEzlL1oexYeuDEQjH5j9
SGFET Nanowire PLL design:
https://drive.google.com/open?id=11aUuht1qpGR8_nj85TnPhnZkIp3dgVg7
[Thesis] "DESIGN OF A PHASE LOCKED LOOP BASED CLOCKING CIRCUIT FOR HIGH SPEED SERIAL LINK APPLICATIONS" by RISHI RATAN:
http://emlab.uiuc.edu/jose/Theses/Ratan.pdf
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