Chisel/Firrtl execution engine

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX