• 3
• 0
• 0

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

• 3
• 0
• 0

systemc-compiler

Intel Compiler for SystemC

• 3
• 0
• 0

rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

• 3
• 0
• 0

chisel

Chisel: A Modern Hardware Design Language

• 3
• 0
• 0

f4pga-database-visualizer

• 3
• 0
• 0

caravel-swerv-el2

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

• 3
• 0
• 0

aib-phy-generator

AIB Generator: Analog hardware compiler for AIB PHY

• 3
• 0
• 0

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

• 2
• 0
• 0

VeeR-EL2-Tock

• 2
• 0
• 0

rocket-uncore

• 2
• 0
• 0

OmnixtendEndpoint

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

• 2
• 0
• 0

firtool-resolver

• 2
• 0
• 0

chisel-nix

Nix template for the chisel-based industrial designing flows.

• 2
• 0
• 0

caliptra-ss

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

• 2
• 0
• 0

chisel-template

A template project for beginning new Chisel work

• 2
• 0
• 0

caliptra-cfi

Code-flow Integrity module to mitigate glitches and fault injections

• 3
• 0
• 0

firrtl-spec

The specification for the FIRRTL language

• 3
• 0
• 0

chisel3

Chisel: A Modern Hardware Design Language

• 3
• 0
• 0

fpga-tool-perf

FPGA tool performance profiling

• 3
• 0
• 0

f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.