@piyo_huang
Impossible is not something that can't be done. It's something that hasn't been done before.
soc_reeg_gen脚本主要实现基于寄存器表单生成verilog代码的功能。
用状态机实现对序列8'b1011_0111的检测，当检测到这个序列时，输出detect_flag置高，表示检测成功。
从零开始riscv的编程之旅！
