Forked from sora/ovs-hw
An open source hardware engine for Open vSwitch on FPGA
The sources of the online SpinalHDL doc
10/100/1000M Ethernet tester
SpinalHDL-tutorial based on Jupyter Notebook
A basic SpinalHDL project
A FPGA friendly 32 bit RISC-V CPU implementation
Open Programmable Acceleration Engine
Open source, high performance, FPGA-based NIC
Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
Verilator open-source SystemVerilog simulator and lint system
Study PCIe, using EasyGX dev-board