clone 的https://github.com/pConst/basic_verilog
clone https://github.com/mcjtag/axis-uart.git
clone https://github.com/strath-sdr/RFSoC-Book.git
clone https://github.com/datahackor/TOMLABv4.6.git
网上把改工程承的p文件转换为m文件
clone https://github.com/hamsternz/DisplayPort_Verilog.git
clone https://github.com/Digilent/vivado-library.git
clone https://gitlab.nikhef.nl/franss/wupper.git
clone https://github.com/alexforencich/verilog-cam.git
clone https://github.com/alexforencich/verilog-uart.git
clone https://github.com/alexforencich/verilog-i2c.git
Verilog/SystemVerilog simulator
clone的https://github.com/alexforencich/verilog-axi
clone的https://github.com/fpgadeveloper/fpga-drive-aximm-pcie.git