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whik/UART_Demo_Verilog

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UART_Demo_Verilog.gise 5.61 KB
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whik 提交于 6年前 . 新建串口工程
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="UART_Demo_Verilog.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="my_uart_rx_stx_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="my_uart_rx_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="my_uart_rx_tb_stx_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="uart_tx_8bit_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_tx_8bit_tb_stx_beh.prj"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_tx_demo_tb_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="uart_tx_demo_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="uart_tx_demo_tb_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1566129297" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1566129297">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566559360" xil_pn:in_ck="4548913797685829157" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1566559360">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="HDL/my_uart_rx.v"/>
<outfile xil_pn:name="HDL/my_uart_rx_tb.v"/>
<outfile xil_pn:name="HDL/uart_tx_8bit.v"/>
<outfile xil_pn:name="HDL/uart_tx_8bit_tb.v"/>
<outfile xil_pn:name="HDL/uart_tx_demo.v"/>
<outfile xil_pn:name="HDL/uart_tx_demo_tb.v"/>
</transform>
<transform xil_pn:end_ts="1566559360" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6967272896663262999" xil_pn:start_ts="1566559360">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566559360" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8206386595971824853" xil_pn:start_ts="1566559360">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
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<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566559361" xil_pn:in_ck="4548913797685829157" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1566559360">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="HDL/my_uart_rx.v"/>
<outfile xil_pn:name="HDL/my_uart_rx_tb.v"/>
<outfile xil_pn:name="HDL/uart_tx_8bit.v"/>
<outfile xil_pn:name="HDL/uart_tx_8bit_tb.v"/>
<outfile xil_pn:name="HDL/uart_tx_demo.v"/>
<outfile xil_pn:name="HDL/uart_tx_demo_tb.v"/>
</transform>
<transform xil_pn:end_ts="1566559366" xil_pn:in_ck="4548913797685829157" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8214492361355235245" xil_pn:start_ts="1566559361">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="uart_tx_demo_tb_beh.prj"/>
<outfile xil_pn:name="uart_tx_demo_tb_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1566559366" xil_pn:in_ck="7787592764972238654" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-3941622807282174256" xil_pn:start_ts="1566559366">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="uart_tx_demo_tb_isim_beh.wdb"/>
</transform>
</transforms>
</generated_project>
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https://gitee.com/whik/UART_Demo_Verilog.git
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whik
UART_Demo_Verilog
UART_Demo_Verilog
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