• 1
• 0
• 0

ynxing/PyVerilog

• 1
• 0
• 2

ynxing/8-bits-RISC-CPU-Verilog

• 1
• 0
• 0

ynxing/verilog-vcd-parser

• 1
• 0
• 0

ynxing/cdc

• 1
• 1
• 1

ynxing/async_fifo

• 1
• 0
• 1

ynxing/fpu

• 1
• 0
• 0

ynxing/DisplayPort_Verilog

• 1
• 0
• 0

ynxing/verilog-parser

• 1
• 0
• 0

ynxing/uart

• 1
• 0
• 0

ynxing/caravel_fasoc

soc

• 1
• 0
• 0

ynxing/abc

逻辑优化

• 1
• 0
• 0

ynxing/yosys_openfpga

• 1
• 2
• 0

ynxing/tinyAES

AES 128 256

• 1
• 0
• 0

ynxing/OpenFPGA_tool

• 1
• 0
• 0

ynxing/SOFA

• 1
• 0
• 0

ynxing/pyAesCrypt

AES by python3

• 2
• 0
• 0

ynxing/OpenROAD

开源EDA工具链

• 1
• 1
• 0

ynxing/openfpga

openfpga

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• 0
• 0

ynxing/vtr-with-yosys

############################################################################## vtr-with-yosys ############################################################################## This is a work-in-progress fork of VTR7.0 (at least what I think is VTR7.0!) but supporting Yosys instead of ODIN_II as its front end. This Yosys front-end plumbing was done as part of the VTR-to-Bitstream V2.0 project, and was mostly taken from there, but without any of the destructive back-end mods I made for VPR to supp

• 1
• 0
• 0

ynxing/python-symbiflow-v2x

Verilog to Routing XML file generation from Verilog (python-symbiflow-v2x)