• 1
• 0
• 0

ynxing/vtr-verilog-to-routing

The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development

• 1
• 3
• 0

ynxing/ecc

ECC verilog 搬运github

• 1
• 0
• 0

ynxing/axi4_vip

• 1
• 0
• 0

ynxing/lemon

lemon1.3.1版本，用来生成liblemon.a静态库，安装流程为mkdir build，cd build，cmake ..，make（到这里就已经生成静态库了，可根据需要选择下面是否安装），make install（可选）

• 1
• 0
• 0

ynxing/learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V Mission statement: create teaching material for FPGAs, processor design and RISC-V, using around $40 per students.

• 1
• 0
• 0

ynxing/FPGA教程

• 1
• 0
• 0

ynxing/caravel

• 1
• 0
• 0

ynxing/ThunderScope

• 1
• 0
• 0

ynxing/ES203-COA-CNN

• 1
• 0
• 0

ynxing/MNIST_CNN_HDL

• 1
• 0
• 0

ynxing/CNN_Core