https://github.com/briansune/AD9361-FM-Radio-Verilog-LVDS.git
https://github.com/briansune/AD9361-FM-Radio-Verilog-CMOS.git
rtklibexplorer的demo5分支:https://github.com/rtklibexplorer/RTKLIB.git
通信原理课程设计,直接序列扩频通信系统仿真设计 MATLAB实现 ①实现基带信号生成,扩频码生成,扩频过程,调制,信号经过信道,解调,解 扩,计算误码率。 ②实现接收端的伪码捕获跟踪(忽略载波跟踪问题);捕获算法实现(例如:FFT 快速伪码捕获算法),码跟踪环的实现(例如:超前-滞后环) ③仿真时需注意发射端的伪码序列与接收端的伪码序列需保持不同步,通过②的 实现,完成伪码的同步。
基于纯Verilog实现的FOC控制器,三环均已实现,并且提供配套的上位机进行系统调试
cambriocn tensorflow训练和推理模型集合
A software receiver based on the receiver in "A software-defined GPS and Galileo Receiver", but this receiver is written in C, not Matlab
Open source GPS receiver based on USRP and GN3S
My working copy of SoftGNSS with sundry modifications