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mu/tt05-tdc-hsc

tinyTapeout是一个教育项目，旨在使在真正的芯片上制造数字设计比以往任何时候都更容易、更便宜。

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mu/Timestamp_TDC1

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mu/TDC-CMOS-Designs

Time-to-Digital Converter (TDC) CMOS Designs

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mu/TDC-on-a-Cyclone-V

on a Cyclone V

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mu/TDC-based-Security-Primitive

TDC based Security Primitive (in Verilog)

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mu/freeCodeCamp forked from open_source/freeCodeCamp

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mu/jTDC

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mu/zynq_tdc2

ZYNQ Time-to-digital converter

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mu/OpenTDC

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mu/tdc-fpga2

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mu/PLI_TDC_for_CAN

PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter

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mu/TDC2

Verilog implementation of a tapped delay line TDC

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mu/FpgaTDC

his FPGA project measures time delay with high precision.

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mu/serdes-tdc

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mu/Sigma Delta ADC数模混合电路模型与FPGA实现 forked from xiaowuzxc/Sigma Delta ADC数模混合电路模型与FPGA实现

Σ-Δ(Sigma-Delta)ADC模型，Sigma Delta 移植来自lattice提供的方案，实现模数转换

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mu/Digital Phase-lock Amplifier Based on FPGA forked from Maplestoryz/Digital Phase-lock Amplifier Based on FPGA

高精度数字锁相放大器

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mu/DigitalLockInAmplifier forked from aheck/DigitalLockInAmplifier

Verilog实现数字锁相放大器

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mu/verilog-counter forked from QuantumBird/verilog-counter

verilog实现计数器

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mu/Counter_8255A forked from fubin/Counter_8255A

A 8255A Timer Counter, Written in Verilog.

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mu/frequency_capture forked from RIU/frequency_capture

基于FPGA的微弱信号快速频率捕获