Hummingbirdv2 E203 Core

Hummingbirdv2 E203 RISC-V processor is mainly used for embedded application with low power and area consumption.

Features

The features of Hummingbirdv2 E203 core are as follows.

• RISC-V RV32IMAC or RV32EMAC ISA supported
• 2-Stage Pipeline
• Machine Mode only
• Configurable
• "RISC-V External Debug Support Version 0.11nov12" supported
• NICE(Nuclei Instruction Co-unit Extension) supported

Hierarchy

The hierarchy of Hummingbirdv2 E203 core implementation is shown in the diagram below, and the function of each modules is listed in the table below.

Hierarchy of Hummingbirdv2 E203 core implementation

Configurable

Hummingbirdv2 E203 core is configurable, and user can achieve different implementation by modifying the config.v file (in e203_hbirdv2/rtl/e203/core directory). Detailed config informations can be found in the table below.

Pipeline Structure

The pipeline structure of E203 core is shown in the diagram below.

Pipeline structure of Hummingbirdv2 E203 core

• First stage: Fetch(IFU)
• Second stage: Decode(EXU), Execute(EXU), Write Back(WB)
• Other stage: Memory Access(LSU)

NICE

Introduction

E203 core supports configurable NICE(Nuclei Instruction Co-unit Extension) which could be used to create user-defined instructions. NICE enables the integration of custom hardware co-units that improve domain-specific performance while reducing power consumption.

Co-unit connected by the NICE interface protocol (Hereinafter referred to as NICE-Core) is an independent module outside the Master E203 Core.

NICE Instruction Format

In order to facilitate user to extend custom instructions, RISC-V ISA predefines 4 groups of custom instruction types in 32-bit instructions (Custom-0, Custom-1, Custom-2, Custom-3), each with its own opcode, as shown in the table below.

In E203 Core, user can use these 4 custom instruction groups (Custom-0, Custom-1, Custom-2, Custom-3) for NICE extensions, the following diagram shows the detail of NICE instruction format, and the detailed description of each field in NICE instruction is shown in the table below.

NICE instruction format

NICE Interface

NICE interface has 4 channels, request channel, response channel, memory request channel and memory response channel. The detailed description of each channels are shown in the table below.

NICE Instruction Handling

Before instruction sent to NICE-Core through the NICE interface, it is decoded by E203 processor core and marked as a NICE instruction, at the same time rs1 and rs2 registers are read for the NICE interface if needed.

In case there is a dependency between NICE instruction and previous unfinished instruction, the pipeline would be stalled until the dependency being eliminated. With this mechanism, NICE instruction behaves just like a general instruction from E203 processor core.

NICE request channel confirms a transfer by nice_req_valid and nice_req_ready handshaking. nice_req_valid and other request information should keep stable until nice_req_ready signal is HIGH.

After NICE-Core completes processing, it sends the responese to E203 processor core through NICE response channel.

NICE Memory Access

NICE-Core could access memory through the NICE interface which contains memory request channel and memory response channel.

In memory request channel, NICE-Core sends ICB request including nice_icb_cmd_valid, nice_icb_cmd_addr, nice_icb_cmd_size, nice_icb_cmd_read and nice_icb_cmd_wdata (if it's a write operation), then these signals are waiting for nice_icb_cmd_ready from E203 processor core. Once valid-ready handshakes successfully, E203 processor core processes the memory access operation with its LSU pipe.

In memory response channel, E203 processor core sends nice_icb_rsp_valid and nice_icb_rsp_rdata (if it is a read operation) to NICE-Core and waits for nice_icb_rsp_ready.

While the NICE-Core is going to access memory, nice_mem_holdup signal should be set to HIGH and keep HIGH until NICE-Core finishes all nice memory accesses. This mechanism blocks the following load and store instruction, which can avoid some deadlock scenarios. With the help of nice_mem_holdup, NICE-Core can kick off one or several memory accesses at any time before the NICE instruction is finished.

Typical NICE Operation Examples

NICE-Core multi-cycle processing

NICE-Core access memory

Illegal NICE instruction