A minimal GPU design in Verilog to learn how GPUs work from the ground up

SSRV (Super-scalar RISC-V) - Super-scalar Out-of-Order (OoO) RV32IMC CPU core, 6.4 CoreMark/MHz.

A completely configurable RISC-V Out of Order Core with a base model geared towards maximizing performance

The code for Leveled Packed Memory Array for GPU

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Eclipse ThreadX is an advanced real-time operating system (RTOS) designed specifically for deeply embedded applications.