Watch ustcwen/ADCTest forked from mirrors_MediaArea/ADCTest

Watch ustcwen/ADC学习资料 forked from Lemon_Orange/ADC学习资料

Watch ustcwen/Sigma Delta ADC数模混合电路模型与FPGA实现 forked from xiaowuzxc/Sigma Delta ADC数模混合电路模型与FPGA实现

Σ-Δ(Sigma-Delta)ADC模型，Sigma Delta 移植来自lattice提供的方案，实现模数转换

Watch ustcwen/Digital-Calibration-of-SAR-ADC forked from 李超/Digital-Calibration-of-SAR-ADC

Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)

Watch ustcwen/Analog-Design-of-1.9-GHz-PLL-system forked from 李超/Analog-Design-of-1.9-GHz-PLL-system

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

Watch ustcwen/逐次逼近型SAR ADC数模混合电路模型与FPGA实现 forked from xiaowuzxc/逐次逼近型SAR ADC数模混合电路模型与FPGA实现

逐次逼近型SAR ADC使用广泛，本工程使用模拟元件与FPGA搭建SAR ADC电路模型，帮助初学者用一个实际案例来学习。

Watch ustcwen/ustcbeamer_blue

蓝色主题beamer