逐次逼近型SAR ADC使用广泛，本工程使用模拟元件与FPGA搭建SAR ADC电路模型，帮助初学者用一个实际案例来学习。

Σ-Δ(Sigma-Delta)ADC模型，Sigma Delta 移植来自lattice提供的方案，实现模数转换

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)

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