@wangchaosun
wangchaosun 暂无简介
some tools 's configuration file for ic design / verification .
Verilog/SystemVerilog Testbench generator
ctl: axi bus-function-model
verification demo in systemverilog.
learning from "https://github.com/carlosedp/chiselv"
common transaction library for ready in valid-ready protocol.
TinyMaix学习！origin: https://github.com/sipeed/TinyMaix/tree/main
SystemVerilog/UVM 's common transaction library
验证虚拟项目mcdf
hardware accelerator for lightweight neural networks
