Starting process: module

Starting process: 

SCUBA, Version Diamond (64-bit) 3.11.0.396.4
Fri Jan 10 19:55:33 2020

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n Multiplier -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type dspmult -simple_portname -pfu_mult -widtha 12 -widthb 12 -widthp 24 -signed -PL_stages 1 -input_reg -output_reg -clk0 -ce0 -rst0 
    Circuit name     : Multiplier
    Module type      : dspmult_a
    Module Version   : 4.9
    Ports            : 
	Inputs       : Clock, ClkEn, Aclr, DataA[11:0], DataB[11:0]
	Outputs      : Result[23:0]
    I/O buffer       : not inserted
    EDIF output      : Multiplier.edn
    Verilog output   : Multiplier.v
    Verilog template : Multiplier_tmpl.v
    Verilog testbench: tb_Multiplier_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : Multiplier.srp
    Estimated Resource Usage:
            LUT : 216
            Reg : 100

END   SCUBA Module Synthesis

File: Multiplier.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0