/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.0.396.4 */
/* Module Version: 4.9 */
/* Fri Jan 10 19:55:33 2020 */

/* parameterized module instance */
Multiplier __ (.Clock( ), .ClkEn( ), .Aclr( ), .DataA( ), .DataB( ), 
    .Result( ));