[Device]
Family=machxo2
PartType=LCMXO2-7000HE
PartName=LCMXO2-7000HE-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
CoreRevision=5.8
ModuleName=PLL
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=01/24/2020
Time=21:01:21

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=None
Order=None
IO=0
mode=Frequency
CLKI=8
CLKI_DIV=1
BW=0.764
VCO=480.000
fb_mode=CLKOP
CLKFB_DIV=10
FRACN_ENABLE=0
FRACN_DIV=0
DynamicPhase=STATIC
ClkEnable=0
Standby=0
Enable_sel=0
PLLRst=0
PLLMRst=0
ClkOS2Rst=0
ClkOS3Rst=0
LockSig=0
LockStk=0
WBProt=0
OPBypass=0
OPUseDiv=0
CLKOP_DIV=6
FREQ_PIN_CLKOP=80
OP_Tol=0.1
CLKOP_AFREQ=80.000000
CLKOP_PHASEADJ=0
CLKOP_TRIM_POL=Rising
CLKOP_TRIM_DELAY=0
EnCLKOS=0
OSBypass=0
OSUseDiv=0
CLKOS_DIV=1
FREQ_PIN_CLKOS=100
OS_Tol=0.0
CLKOS_AFREQ=
CLKOS_PHASEADJ=0
CLKOS_TRIM_POL=Rising
CLKOS_TRIM_DELAY=0
EnCLKOS2=0
OS2Bypass=0
OS2UseDiv=0
CLKOS2_DIV=1
FREQ_PIN_CLKOS2=100
OS2_Tol=0.0
CLKOS2_AFREQ=
CLKOS2_PHASEADJ=0
EnCLKOS3=0
OS3Bypass=0
OS3UseDiv=0
CLKOS3_DIV=1
FREQ_PIN_CLKOS3=100
OS3_Tol=0.0
CLKOS3_AFREQ=
CLKOS3_PHASEADJ=0

[Command]
cmd_line= -w -n PLL -lang verilog -synth lse -arch xo2c00 -type pll -fin 8 -fclkop 80 -fclkop_tol 0.1 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1