@wangchaosun
wangchaosun 暂无简介
some tools 's configuration file for ic design / verification .
Verilog/SystemVerilog Testbench generator
ctl: axi bus-function-model
verification demo in systemverilog.
learning from "https://github.com/carlosedp/chiselv"
common transaction library for ready in valid-ready protocol.
TinyMaix学习！origin: https://github.com/sipeed/TinyMaix/tree/main
SystemVerilog/UVM 's common transaction library
验证虚拟项目mcdf
hardware accelerator for lightweight neural networks
芯片前端萌新培训虚拟项目
最全的CRC算法
spinalhdl journey
一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
the uart system for test
2024华为软件精英挑战赛！
2023FPGA暑期学校
我的picgo
帮你画verilog代码的模块接口图
TearPoint
