GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
ESP32无线调试器,成本低廉,能无线调试Xilinx FPGA。受到Vivado的直接支持,具有智能配网,显示IP等功能。基于Arduino开发,可移植性强,支持ESP32任意型号。
Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.
fesvr-zynq searching result for google.
https://github.com/whik/cortex_m3_on_xc7a100t.git
https://github.com/quanzaihh/Neural-Network-Accelerator.git
Workspace for zhaomeijing, include PC-Server/Platform/Account. |---Novauto |---YUSUR |---FPGAs(Zynq/Zynq-MPSoC) |---ICs
【关键词】icap,deviceid,DEVICE-ID 【主要功能】基于AMD-Xilinx的ICAP原语,在KUP系列上实现了读取DEVICE-ID的功能。更多信息请参考icap_crc_prj/ndpp_icap_crc_prj/README.md。
Example designs for FPGA Drive FMC
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
《神经网络设计》 - sklearn简单入门 - pyttorch图像分类入门 - LeNet,AlexNet,VGG,ResNet - Cifar-10